The following ports from the UltraScale+ Integrated Block for PCIe IP that are not available in the Versal Adaptive SoC Integrated Block for PCIe IP.
Name | I/O | Width | Notes |
---|---|---|---|
drp_di | I | 16 | PCIe DRP ports are replaced with APB3 ports in Versal adaptive SoC. For port details, see Table 1. |
drp_do | O | 16 | |
drp_rdy | O | 1 | |
drp_we | I | 1 |