Basic Tab - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The Basic page with Advanced mode selected (shown in the following figure) includes additional settings. The following parameters are visible on the Basic page when the Advanced mode is selected.

Figure 1. Basic Tab, Advanced Mode

Core Clock Frequency

For Gen1 and Gen2 it is 250 MHz always.

For Gen3 and Gen4 it is 500 MHz always.

Enable Parity
Enables Parity on TX/RX interfaces including MSI-X.
PCIe APB3 Ports
When checked, enables the PCIe APB3 interface.
PCIe Link Debug
This enables the link debug option to be activated.
Enable Lane Reversal
This enables the lane reversal feature.