| Name | I/O | Width | Description |
|---|---|---|---|
| cfg_interrupt_int | I | 4 | Configuration INTx Vector: When the core is configured as EP,
these four inputs are used by the user application to signal an interrupt from any
of its PCI Functions to the RC using the Legacy
PCI Express Interrupt Delivery mechanism of
PCI Express. These four inputs correspond to
INTA, INTB, INTC, and INTD of the PCI bus,
respectively. Asserting one of these signals causes the core to send out an
Assert_INTx message, and deasserting the signal causes the core to transmit a
Deassert_INTx message. Note: When PASID_CAP_ON = TRUE,
this pin is not available for use.
|
| cfg_interrupt_sent | O | 1 | Configuration INTx Sent: A pulse on this output indicates that the core has sent an INTx Assert or Deassert message in response to a change in the state of one of the cfg_interrupt_int inputs. |
| cfg_interrupt_pending | I |
4 in PL-PCIE4 8 in PL-PCIE5 |
Configuration INTx Interrupt Pending: Per Function indication
of a pending interrupt from the user. cfg_interrupt_pending[0] corresponds to
Function #0. Each of these inputs is connected to the Interrupt Pending bits of the
PCI Status Register of the corresponding
Function. Note: When PASID_CAP_ON = TRUE,
this pin is not available for use.
|