See the cfg_interrupt_msi* and cfg_interrupt_msix_* descriptions in the tables in Configuration Interrupt Controller Interface.
The core supports sending interrupt requests as either legacy, Message MSI, or MSI-X interrupts. The mode is programmed using the MSI Enable bit in the Message Control register of the MSI Capability Structure and the MSI-X Enable bit in the MSI-X Message Control register of the MSI-X Capability Structure.
The state of the MSI Enable and MSI-X Enabled bits is reflected by the
cfg_interrupt_msi_enable and cfg_interrupt_msix_enable outputs, respectively. The
following table describes the Interrupt Mode to which the device has been programmed,
based on the cfg_interrupt_msi_enable and cfg_interrupt_msix_enable outputs of the core.
| cfg_interrupt_msixenable=0 | cfg_interrupt_msixenable=1 | |
|---|---|---|
|
cfg_interrupt_msi_enable = 0 |
Legacy Interrupt (INTx) mode. The cfg_interrupt interface only sends INTx messages. |
MSI-X mode. MSI-X interrupts can be generated using the
|
|
cfg_interrupt_msi_enable = 1 |
MSI mode. The cfg_interrupt interface only sends MSI interrupts (MWr TLPs). |
Undefined. System software is not supposed to permit this. However, the cfg_interrupt interface is active and sends MSI interrupts (MWr TLPs) if you choose to do so. |
The MSI Enable bit in the MSI control register, the MSI-X Enable bit in the MSI-X Control register, and the Interrupt Disable bit in the PCI Command register are programmed by the Root Complex. The user application has no direct control over these bits.
The Internal Interrupt Controller in the core only generates Legacy
Interrupts and MSI Interrupts. MSI-X Interrupts need to be generated by the user
application and presented on the transmit AXI4-Stream
interface. The status of cfg_interrupt_msi_enable
determines the type of interrupt generated by the internal Interrupt Controller:
If the MSI Enable bit is set to a 1, the core generates MSI requests by sending Memory Write TLPs. If the MSI Enable bit is set to 0, the core generates legacy interrupt messages as long as the Interrupt Disable bit in the PCI Command register is set to 0.
-
cfg_interrupt_msi_enable= 0: Legacy interrupt -
cfg_interrupt_msi_enable= 1: MSI - Command register bit 10 = 0: INTx interrupts enabled
- Command register bit 10 = 1: INTx interrupts disabled (requests are blocked by the core)
The user application can monitor cfg_function_status to check whether INTx interrupts are enabled or
disabled. For more information, see Configuration Status Interface.
The core can be configured to advertise multiple interrupt modes support,
however at runtime, only one interrupt mode can be enabled at a time across all
functions. AMD does not recommend enabling multiple interrupt modes at
once, however in the event that MSI and MSI-X interrupts simultaneous enablement cannot
be avoided, MSI-X interrupt must be implemented externally of the core and interrupt
packet is formed and sent through the Requester Request Interface Port (s_axis_rq).
The user application requests interrupt service in one of two ways, each of which is described in the following section.