Requester Request Interface Operation (512-bit) - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The following figure illustrates the signals associated with the requester request interface of the core. The core delivers each TLP on this interface as an AXI4-Stream packet. The packet starts with a 128-bit descriptor, followed by data in the case of TLPs with a payload.

The requester request interface supports two distinct data alignment modes for transferring payloads, which are set during core customization in the AMD Vivado™ IDE. In the Dword-aligned mode, the user logic must provide the first Dword of the payload immediately after the last Dword of the descriptor. It must also set the bits in first_be[7:0] to indicate the valid bytes in the first Dword and the bits in last_be[7:0] (both part of the s_axis_rq_tuser bus) to indicate the valid bytes in the last Dword of the payload. In the address-aligned mode, the user logic must start the payload transfer in the beat following the last Dword of the descriptor, and its first Dword can be in any of the possible Dword positions on the datapath. The user application communicates the offset of the first Dword on the datapath using the signals addr_offset[3:0] in s_axis_rq_tuser. As in the case of the Dword-aligned mode, the user application must also set the bits in first_be[7:0] to indicate the valid bytes in the first Dword and the bits in last_be[7:0] to indicate the valid bytes in the last Dword of the payload. In Straddled case, addr_offset[3:2], first_be[7:4], and last_be[7:4] are used to indicate second TLP information while addr_offset[1:0], first_be[3:0], and last_be[3:0] are used to indicate the first TLP information on that data beat.

Figure 1. Requester Request Interface Signals

The interface also supports a straddle option that allows the transfer of up to two TLPs in the same beat across the interface. The straddle option can be used only with the Dword-aligned mode, and is not supported when using the 128-bit address aligned mode. The descriptions in the sections below assume a single TLP per beat. The operation of the interface with the straddle option enabled is described in Straddle Option on RQ Interface.