Reset - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

This core uses the same reset routing as the AMD UltraScale+ devices integrated block, and reset is connected to the input pin. Alternatively, sys_rst can be connected from CIPS MIO 38. To use CIPS MIO 38 as a reset source, use either of these methods:

  • Enter the following command to enable CIPS before opening the example design:
    set_property config.insert_cips {true} [get_ips pcie_versal_0]
  • Set the property in your block design before running block automation:
    set_property config.insert_cips {true} [get_bd_cells pcie_versal_0]

The connection is like the following diagram, mio_pl_38 is connected to sys_reset of pcie_versal, phy_rst_n of pcie_phy, and as an output for user application to use:

Figure 1. Reset Connection