MSI Interrupt Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. MSI Interrupt Interface Port Descriptions
Name I/O Width Description
cfg_interrupt_msi_enable O

4 in PL-PCIE4

1 in PL-PCIE5

Configuration Interrupt MSI Function Enabled

Indicates that the Message Signaling Interrupt (MSI) messaging is enabled, per Function. These outputs reflect the setting of the MSI Enable bits in the MSI Control Register of Physical Functions 0 – 3.

Note: In PL-PCIE5, only the Function 0 setting is indicated. For subsequent functions, the wrreq interface is used.
cfg_interrupt_msi_int I 32 Configuration Interrupt MSI Vector

When configured in the Endpoint mode to support MSI interrupts, these inputs are used to signal the 32 distinct interrupt conditions associated with a PCI Function (Physical or Virtual) from the user logic to the core. The Function number must be specified on the input cfg_interrupt_msi_function_number. After placing the Function number on the input cfg_interrupt_msi_function_number, the user logic must activate one of these signals for one cycle to transmit an interrupt. The user logic must not activate more than one of the 32 interrupt inputs in the same cycle. The core internally registers the interrupt condition on the 0-to-1 transition of any bit in cfg_interrupt_msi_int. After asserting an interrupt, the user logic must wait for the cfg_interrupt_msi_sent or cfg_interrupt_msi_fail indication from the core before asserting a new interrupt.

cfg_interrupt_msi_function_number I

8 in PL-PCIE4

16 in PL-PCIE5

Configuration MSI Initiating Function in PL-PCIE4.

Indicates the Endpoint Function # initiating the MSI interrupt.

  • 8'h00 – 8'h03: PF 0 – PF 3
  • 8'h04 – 8'hFF: VF 0 – VF 252
  • Other encodings are reserved.

Configuration MSI Initiating Function in PL-PCIE5.

Indicates the Endpoint function # initiating the MSI transaction. 16'h0000-16'h100F is the supported range. Other encodings are reserved.

cfg_interrupt_msi_sent O 1 Configuration Interrupt MSI Interrupt Sent

The core generates a one-cycle pulse on this output to signal that an MSI or MSI-X interrupt message has been transmitted on the link. The user logic must wait for this pulse before signaling another interrupt condition to the core.

cfg_interrupt_msi_fail O 1 Configuration Interrupt MSI Interrupt Operation Failed

A one-cycle pulse on this output indicates that an MSI interrupt message was aborted before transmission on the link. The user logic must retransmit the MSI interrupt in this case.

cfg_interrupt_msi_mmenable O

12 in PL-PCIE4

3 in PL-PCIE5

Configuration Interrupt MSI Function Multiple Message Enable

When the core is configured in the Endpoint mode to support MSI interrupts, these outputs are driven by the 'Multiple Message Enable' bits of the MSI Control Register associated with Physical Functions. These bits encode the number of allocated MSI interrupt vectors for the corresponding Function. Bits [2:0] correspond to Physical Function 0, bits [5:3] correspond to PF 1, and so on. The valid encodings of the 3 bits are:

  • 000b: 1 vector
  • 001b: 2 vectors
  • 010b: 4 vectors
  • 011b: 8 vectors
  • 100b: 16 vectors
  • 101b: 32 vectors
Note: In PL-PCIE5, only the Function 0 setting is indicated. For subsequent functions, the wrreq interface is used.
cfg_interrupt_msi_pending_status I 32 Configuration MSI Interrupt Pending Status

These inputs are provided for the user to indicate the interrupt pending status of the MSI interrupts associated with the Physical Functions. When the status of a MSI interrupt associated with a PF changes, the user must place the new interrupt status on these inputs, along with the corresponding Function number on the cfg_interrupt_msi_pending_status_function_num input, and activate the cfg_interrupt_msi_pending_status_data_enable input for one cycle. The core latches the new status in its MSI Pending Bits Register of the corresponding Physical Function.

cfg_interrupt_msi_pending_status_function_num I

2 in PL-PCIE4

3 in PL-PCIE5

Configuration Interrupt MSI Pending Target Function Number
  • 00 = PF 0
  • 01 = PF 1
  • 10 = PF 2
  • 11 = PF 3
  • 100 = PF 4
  • 101 = PF 5
  • 110 = PF 6
  • 111 = PF 7

This input is used to identify the Function number when the user places interrupt status on the cfg_interrupt_msi_pending_status inputs.

cfg_interrupt_msi_pending_status_data_enable I 1 Configuration Interrupt MSI Pending Data Valid

The user application asserts this signal together with cfg_interrupt_msi_pending_status and cfg_interrupt_msi_pending_status_function_num values to update the MSI Pending Bits in the corresponding function.

cfg_interrupt_msi_mask_update O 1 Configuration Interrupt MSI Function Mask Updated

The SR-IOV core asserts this for 1 cycle when the MSI Mask Register of any enabled PFs has changed its value. You can read the new mask settings from the cfg_interrupt_msi_data outputs.

cfg_interrupt_msi_select I

2 in PL-PCIE4

3 in PL-PCIE5

Configuration Interrupt MSI Select

These inputs are used to select the Function number for reading the MSI Mask Register setting from the core. Values 0 – 7 correspond to Physical Functions 0 – 7, respectively. The mask MSI Mask Register contents of the selected PF appear on the output cfg_interrupt_msi_data after one cycle.

cfg_interrupt_msi_data O 32 Configuration Interrupt MSI Data

These output reflect the MSI Mask Register setting of the Physical Function selected by the cfg_interrupt_msi_select input.

cfg_interrupt_msi_attr I 3 Configuration Interrupt MSI TLP Attribute

These bits enable you to set the Attribute bits that are used for both MSI and MSI-X interrupt requests.

  • Bit 0 is the No Snoop bit.
  • Bit 1 is the Relaxed Ordering bit.
  • Bit 2 is the ID-Based Ordering bit.

The core samples these bits on a 0-to-1 transition on cfg_interrupt_msi_int bits (when using MSI) or cfg_interrupt_msix_int (when using MSI-X).

cfg_interrupt_msi_tph_present I 1

Configuration Interrupt MSI/MSIX TPH Present.

Indicates the presence of a Transaction Processing Hint (TPH) in the MSI/MSIX interrupt request. The user application must set this bit while asserting cfg_interrupt_msi_int bits or cfg_interrupt_msix_int if it is including a TPH in the MSI or MSIX transaction.

Note: These bits are reserved.
cfg_interrupt_msi_tph_type I 2

Configuration Interrupt MSI/MSIX TPH Type.

When cfg_interrupt_msi_tph_present is 1'b1, these two bits are used to supply the 2-bit type associated with the Hint. The core samples these bits on 0-to-1 transition on cfg_imterrupt_msi_int bits or cfg_interrupt_msix_int.

Note: These bits are reserved.
cfg_interrupt_msi_tph_st_tag I 8

Configuration Interrupt MSI/MSIX TPH Steering Tag.

When cfg_interrupt_msi_tph_present is 1'b1, the Steering Tag associated with the Hint must be placed on cfg_interrupt_msi_tph_st_tag[7:0].

Note: These bits are reserved.