Lane Reversal - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

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1.0 English

The integrated block supports limited lane reversal capabilities and therefore provides flexibility in the design of the board for the link partner. The link partner can choose to lay out the board with reversed lane numbers and the integrated block continues to link train successfully and operate normally. The configurations that have lane reversal support are 16x, x8, and x4 (excluding downshift modes). Downshift refers to the link width negotiation process that occurs when link partners have different lane width capabilities advertised. As a result of lane width negotiation, the link partners negotiate down to the smaller of the advertised lane widths. The following table describes the several possible combinations including downshift modes and availability of lane reversal support.

Table 1. Lane Reversal Support
Integrated Block Advertised Lane Width Negotiated Lane Width Lane Number Mapping (Endpoint Link Partner) Lane Reversal Supported
Endpoint Link Partner
x16 x16 Lane 0... Lane15 Lane15... Lane 0 Yes
x16 x8 Lane 0... Lane7 Lane7... Lane 0 No
x16 x4 Lane 0... Lane3 Lane3... Lane 0 No
x16 x2 Lane 0... Lane1 Lane1... Lane 0 No
x8 x8 Lane 0... Lane 7 Lane 7... Lane 0 Yes
x8 x4 Lane 0... Lane 3 Lane 7... Lane 4 No 1
x8 x2 Lane 0... Lane 3 Lane 7... Lane 6 No 1
x4 x4 Lane 0... Lane 3 Lane 3... Lane 0 Yes
x4 x2 Lane 0... Lane 1 Lane 3... Lane 2 No 1
x2 x2 Lane 0... Lane 1 Lane 1... Lane 0 Yes
x2 x1 Lane 0... Lane 1 Lane 1 No 1
  1. When the lanes are reversed in the board layout and a downshift adapter card is inserted between the Endpoint and link partner, Lane 0 of the link partner remains unconnected (as shown by the lane mapping in this table) and therefore does not link train.