PL PCIE5 Features - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

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1.0 English

The PL PCIE5 features of the Versal™ Adaptive SoC Integrated Block for PCI Express® provides a high-performance PCI Express port that allows for a wide range of user customization.

Features of PL PCIE5 in the Versal device PCI Express block, are listed below:

  • Designed to the PCI Express Base Specification 5.0, Rev. 1.0 and Errata/ECN updates
  • Designed to the CCIX Base Specification v1.1 and Errata/ECN updates
  • PCI Express Endpoint, Legacy Endpoint, Root, or Switch Port Modes
  • Gen1, Gen2, Gen3, Gen4, and Gen5 link speeds up to x16 link width is supported with some limitations in Gen4 and Gen5. For more information, see Table 2.
  • AXI4-Stream Interface to customer logic
    • Configurable 64-bit/128-bit/256-bit/512-bit data path widths
    • Four Independent Initiator/Target, Request/Completion Streams
  • Parity protection on internal logic data paths and data interfaces
  • Advanced Error Reporting (AER) and End-to-End CRC (ECRC)
  • UltraRAM used for Transaction Layer Packet buffering
    • 32 KB replay buffer
    • Configurable 16 KB or 32 KB received posted transaction FIFO
    • Configurable 32 KB or 64 KB received completion transaction FIFO
    • UltraRAM ECC protection feature is used
  • Two Virtual Channel, 8 Traffic Classes
    • VC1 data path limited to Data Link Layer CCIX Interface to fabric
      • VC1 Transaction Layer functionality implemented in soft logic
  • Supports multiple Functions and Single-Root IO Virtualization
    • Up to 8 Physical Functions
    • Up to 4088 Virtual Functions
  • PASID TLP Prefix Capability Supported
  • Built-in lane reversal and receiver lane-lane de-skew
  • 3 x 64-bit or 6 x 32-bit Base Address Registers (BARs) that are fully configurable
    • Expansion ROM BAR supported
  • All Interrupt types are supported
    • INTx
    • 32 multi-vector MSI capability
    • MSI-X capability with up to 16k vectors with optional to use, built-in MSI-X vector tables
  • Built-in Initiator Read Request/Completion Tag Manager
    • Up to 256 or 768 outstanding Initiator Read Request Transactions supported
  • Advanced Peripheral Bus (APB3) port is supported
  • PCIe Extended Capabilities (Optional capabilities)
    • Device Serial Number Capability
    • Virtual Channel Capability
    • ARI Capability
    • SR-IOV Extended Capability Structure
    • Configuration Space Extend Capabilities
    • Address Translation Services (ATS)
    • Page Request Interface (PRI)
    • PASID
    • Feature DLLP
    • CCIX Transport DVSEC via configuration space extension
    • Data Link Layer Feature Extended Capability
    • Physical Layer 16.0 GT/s Extended Capability
    • Physical Layer 32.0 GT/s Extended Capability
    • ACS Extended Capability and ACS Error Logging/Reporting
    • Lane Margining at Receiver Extended Capability