TLP Tasks - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. TLP Tasks
Name Input(s) Description
TSK_TX_TYPE0_CONFIGURATION_READ

tag_

reg_addr_

first_dw_be_

7:0

11:0

3:0

Sends a Type 0 PCI Express Config Read TLP from Root Port Model to reg_addr of Endpoint DUT with tag_ and first_dw_be_ inputs.

Cpld returned from the Endpoint DUT uses the contents of global EP_BUS_DEV_FNS as the completer ID.

TSK_TX_TYPE1_CONFIGURATION_READ

tag_

reg_addr_

first_dw_be_

7:0

11:0

3:0

Sends a Type 1 PCI Express Config Read TLP from Root Port Model to reg_addr_ of Endpoint DUT with tag_ and first_dw_be_ inputs.

CplD returned from the Endpoint DUT uses the contents of global EP_BUS_DEV_FNS as the completer ID.

TSK_TX_TYPE0_CONFIGURATION_WRITE

tag_

reg_addr_

reg_data_

first_dw_be_

7:0

11:0

31:0

3:0

Sends a Type 0 PCI Express Config Write TLP from Root Port Model to reg_addr_ of Endpoint DUT with tag_ and first_dw_be_ inputs.

Cpl returned from the Endpoint DUT uses the contents of global EP_BUS_DEV_FNS as the completer ID.

TSK_TX_TYPE1_CONFIGURATION_WRITE

tag_

reg_addr_

reg_data_

first_dw_be_

7:0

11:0

31:0

3:0

Sends a Type 1 PCI Express Config Write TLP from Root Port Model to reg_addr_ of Endpoint DUT with tag_ and first_dw_be_ inputs.

Cpl returned from the Endpoint DUT uses the contents of global EP_BUS_DEV_FNS as the completer ID.

TSK_TX_MEMORY_READ_32

tag_

tc_

len_

addr_

last_dw_be_

first_dw_be_

7:0

2:0

10:0

31:0

3:0

3:0

Sends a PCI Express Memory Read TLP from Root Port to 32-bit memory address addr_ of Endpoint DUT.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

TSK_TX_MEMORY_READ_64

tag_

tc_

len_

addr_

last_dw_be_

first_dw_be_

7:0

2:0

10:0

63:0

3:0

3:0

Sends a PCI Express Memory Read TLP from Root Port Model to 64-bit memory address addr_ of Endpoint DUT.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

TSK_TX_MEMORY_WRITE_32

tag_

tc_

len_

addr_

last_dw_be_

first_dw_be_

ep_

7:0

2:0

10:0

31:0

3:0

3:0

Sends a PCI Express Memory Write TLP from Root Port Model to 32-bit memory address addr_ of Endpoint DUT.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

The global DATA_STORE byte array is used to pass write data to task.

TSK_TX_MEMORY_WRITE_64

tag_

tc_

len_

addr_

last_dw_be_

first_dw_be_

ep_

7:0

2:0

10:0

63:0

3:0

3:0

Sends a PCI Express Memory Write TLP from Root Port Model to 64-bit memory address addr_ of Endpoint DUT.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

The global DATA_STORE byte array is used to pass write data to task.

TSK_TX_COMPLETION

req_id_

tag_

tc_

len_

byte_count_

lower_addr_

comp_status_

ep_

15:0

7:0

2:0

10:0

2:0

11:0

6:0

-

Sends a PCI Express Completion TLP from Root Port Model to the Endpoint DUT using global RP_BUS_DEV_FNS as the completer ID, req_id_ input as the requester ID.

comp_status_ input can be set to one of the following:

3'b000 = Successful Completion

3'b001 = Unsupported Request

3'b010 = Configuration Request Retry Status

3'b100 = Completer Abort

TSK_TX_COMPLETION_DATA

req_id_

tag_

tc_

len_

byte_count_

lower_addr_

ram_ptr

comp_status_

ep_

15:0

7:0

2:0

10:0

11:0

6:0

RP_BAR_ SIZE:0

2:0

Sends a PCI Express Completion with Data TLP from Root Port Model to the Endpoint DUT using global RP_BUS_DEV_FNS as the completer ID, req_id_ input as the requester ID.

The global DATA_STORE_2 byte array is used to pass completion data to task and the ram_ptr input is used to offset the starting byte within this array.

TSK_TX_MESSAGE

tag_

tc_

len_

data_

message_rtg_

message_code_

7:0

2:0

10:0

63:0

2:0

7:0

Sends a PCI Express Message TLP from Root Port Model to Endpoint DUT.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

TSK_TX_MESSAGE_DATA

tag_

tc_

len_

data_

message_rtg_

message_code_

7:0

2:0

10:0

63:0

2:0

7:0

Sends a PCI Express Message with Data TLP from Root Port Model to Endpoint DUT.

The global DATA_STORE byte array is used to pass message data to task.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

TSK_TX_IO_READ

tag_

addr_

first_dw_be_

7:0

31:0

3:0

Sends a PCI Express I/O Read TLP from Root Port Model to I/O address addr_[31:2] of the Endpoint DUT.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

TSK_TX_IO_WRITE

tag_

addr_

first_dw_be_

data

7:0

31:0

3:0

31:0

Sends a PCI Express I/O Write TLP from Root Port Model to I/O address addr_[31:2] of the Endpoint DUT.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

TSK_TX_BAR_READ

bar_index

byte_offset

tag_

tc_

2:0

31:0

7:0

2:0

Sends a PCI Express one Dword Memory 32, Memory 64, or I/O Read TLP from the Root Port Model to the target address corresponding to offset byte_offset from BAR bar_index of the Endpoint DUT. This task sends the appropriate Read TLP based on how BAR bar_index has been configured during initialization. This task can only be called after TSK_BAR_INIT has successfully completed.

The request uses the contents of global RP_BUS_DEV_FNS as the Requester ID.

TSK_TX_BAR_WRITE

bar_index

byte_offset

tag_

tc_

data_

2:0

31:0

7:0

2:0

31:0

Sends a PCI Express one Dword Memory 32, Memory 64, or I/O Write TLP from the Root Port to the target address corresponding to offset byte_offset from BAR bar_index of the Endpoint DUT.

This task sends the appropriate Write TLP based on how BAR bar_index has been configured during initialization. This task can only be called after TSK_BAR_INIT has successfully completed.

TSK_WAIT_FOR_READ_DATA None  

Waits for the next completion with data TLP that was sent by the Endpoint DUT. On successful completion, the first Dword of data from the CplD is stored in the global P_READ_DATA. This task should be called immediately following any of the read tasks in the TPI that request Completion with Data TLPs to avoid any race conditions.

By default this task locally times out and terminate the simulation after 1000 transaction interface clocks. The global cpld_to_finish can be set to zero so that local timeout returns execution to the calling test and does not result in simulation timeout. For this case test programs should check the global cpld_to, which when set to one indicates that this task has timed out and that the contents of P_READ_DATA are invalid.

TSK_TX_SYNCHRONIZE

first_

active_

last_call_

tready_sw_

-

-

-

-

Waits for assertion of AXI4-Stream Requester Request or Completer Completion Interface Ready signal and synchronizes the output in the log file to each transaction currently active.

first_ input indicates start of packet.

active_ input indicates a transaction is currently in progress.

last_call_ input indicates end of packet.

tready_sw input selects Requester Request or Completer Completion Interface Ready signal.

TSK_BUILD_RC_TO_PCIE_PKT

rc_data_QW0

rc_data_QW1

m_axis_rc_tkeep

m_axis_rc_tlast

63:0

63:0

KEEP_ WIDTH-1:0

-

Converts AXI4-Stream packet at Requester Completion Interface from a Descriptor packet format to PCIe TLP packet format for logging purposes.
TSK_BUILD_CQ_TO_PCIE_PKT

cq_data

cq_be

m_axis_cq_tdata

63:0

7:0

63:0

Converts AXI4-Stream packet at Completer Request Interface from a Descriptor packet format to PCIe TLP packet format for logging purposes.
TSK_BUILD_CPLD_PKT

cq_addr

cq_be

m_axis_cq_tdata

63:0

15:0

63:0

Returns Completion or Completion with Data for Memory Read received from the Endpoint DUT. When the Completer Model is used, the completion produced is split according to Max Payload Size and Read Completion Boundary rules set at the Root Port Model. Completion with Data uses data stored in the global DATA_STORE_2 array.