The AMD Versal™ Adaptive SoC Integrated Block for PCI Express® ( PCIe® ) core is a reliable, high-bandwidth, scalable serial interconnection for use with Versal devices. The core instantiates one of the available programmable logic integrated blocks for PCIe found in the Versal devices.
The following figure shows the block diagram of the core.
Figure 1. Block Diagram for Programmable Logic Integrated Block for
PCIe
The following figure shows the interfaces for the core.
Figure 2. Core Interfaces
