The following figure illustrates the transfer of a Completion TLP received from the link with no associated payload across the requester completion interface. The timing diagrams in this section assume that the Completions are not straddled on the interface. The straddle feature is described in Straddle Option for RC Interface.
The entire transfer of the Completion TLP takes only a single beat on the interface. The
core keeps the signal m_axis_rc_tvalid asserted over the duration of
the packet. The user logic can prolong a beat at any time by pulling down
m_axis_rc_tready. The AXI4-Stream interface
signals m_axis_rc_tkeep (one per Dword position) indicate the valid
descriptor Dwords in the packet. That is, the m_axis_rc_tkeep bits are
set to 1 contiguously from the first Dword of the descriptor until its last Dword. The
signal m_axis_rc_tlast is always asserted, indicating that the packet
ends in its current beat.
The m_axi_rc_tuser bus also includes a signal
is_sop[0], which is asserted in the first beat of every packet. The
user logic are optionally use this signal to qualify the start of the descriptor on the
interface. When the straddle option is not in use, none of the other sop and eop
indications within m_axi_rc_tuser are relevant to the transfer of
Completions.