The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/10/2023 Version 1.0 | |
| 64/128/256-bit Completer Interface | Updated tables. |
| Completions with Error Status (UR and CA) | Updated tables. |
| 64/128/256-bit Requester Interface | Updated tables. |
| 512-bit Completer Interface | Updated tables. |
| Completer Completion Interface Operation (512-bit) | Updated tables. |
| 512-bit Requester Interface | Updated tables. |
| Clock and Reset Signals | Updated Clock and Reset Signals table. |
| Supported Clock Frequencies and Interface Widths | Updated Clock Frequencies and Interface Widths Supported for Various Configurations table. |
| PL PCIE5 Features | Updated features. |
| Limitations | Added new limitations. |
| Completer Request Interface | Updated Completer Request Interface Port Descriptions table. |
| Configuration Management Interface | Updated Configuration Management Interface Port Descriptions table. |
| Configuration Status Interface | Updated Configuration Status Interface Port Descriptions table. |
| Configuration Control Interface | Updated Configuration Control Interface Port Descriptions table. |
| Legacy Interrupt Interface | Updated Legacy Interrupt Interface Port Descriptions table. |
| MSI Interrupt Interface | Updated MSI Interrupt Interface Port Descriptions table. |
| MSI-X Interrupt External Interface | Updated MSI-X Interrupt External Interface Port Descriptions table. |
| Configuration PASID Interface | Updated Configuration PASID Interface Port Descriptions table. |
| New Ports | Updated New Ports in the Versal PL PCIe Core table. |
| GT Quad Locations | Updated GT Locations table. |
| 05/16/2023 Version 1.0 | |
| PL PCIE4 Features | Updated features. |
| PL PCIE5 Features | Updated features. |
| Configuration Status Interface | Updated cfg_local_error_out port description. |
| Features Not Available, or Limited Usage Features | Updated. |
| Features Not Available, or Limited Usage Features | Updated. |
| 11/02/2022 Version 1.0 | |
| PL PCIE5 Features | Added new features. |
| Unsupported Features | Updated unsupported features. |
| Configuration Status Interface | Updated Configuration Status Interface Port Descriptions table. |
| 06/21/2022 Version 1.0 | |
| Limitations | Updated. |
| Migrating from Other Device Cores to PL PCIe5 | Added new section. |
| 04/26/2022 Version 1.0 | |
| General updates | Updated for Versal Premium ACAP support. |
| Debug Guide | New section. |
| Unsupported Features | Updated. |
| 12/20/2021 Version 1.0 | |
| GT Quad Locations | Updated. |
| 10/21/2021 Version 1.0 | |
| Completer Request Descriptor Formats, Completer Completion Descriptor Format, Requester Request Descriptor Formats, Requester Completion Descriptor Format | Added 10b tag bit information. |
| Minimum Device Requirements | Added section. |
| Integrated Block Endpoint Configuration Overview | Updated command. |
| PL PCIe GT Selection | Updated configuration details. |
| 04/15/2021 Version 1.0 | |
| Limitations | Added topic to report known issues in the release. |
| Generating the Core | Add note regarding connecting the PCIe reset pin to the MIO38 pin location using a Tcl command. |
| 01/20/2021 Version 1.0 | |
| Customizing and Generating the Core | Updated GUI figures, and descriptions throughout. |
| Performance and Resource Use | Added section with link to resource use data. |
| Upgrading | New appendix. Added detailed migration information. |
| 11/03/2020 Version 1.0 | |
| General Update | Updated document with correct version 1.0. |
| 07/27/2020 Version 1.0 | |
| Initial AMD release. | N/A |