Initiator Logic - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The function of the initiator block is to generate memory write or memory read TLPs depending on whether an upstream or downstream transfer is selected. The Bus Master DMA design only supports generating one type of a data flow at a single time. The Bus Master enable bit (Bit 2 of PCI Command Register) must be set to initiate TLP traffic upstream. No transactions are allowed to cross the 4K boundary.

The initiator logic generates memory write TLPs when transferring data from the endpoint to system memory. The Write DMA control and status registers specify the address, size, payload content, and number of TLPs to be sent.

All registers are defined in Appendix A: Design Descriptor Registers of Bus Master Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express Solutions (XAPP1052).

The following table shows BMD design file structure for 64/128/256-bit configuration.

Table 1. BMD 64/128/256-bit Design File Structure
File Description
BMD_AXIST.v Top-level design wrapper
BMD_AXIST_EP.v Top-level module
BMD_AXIST_EP_MEM_ACCESS.v Memory access module
BMD_AXIST_EP_MEM.v Memory module
BMD_AXIST_TX_ENGINE.v BMD Transmit engine
BMD_AXIST_RX_ENGINE.v BMD Receive engine
BMD_AXIST_INTR_CTRL.v Interrupt controller
BMD_AXIST_TO_CTRL.v Turn-off controller module

The following table shows BMD design file structure for 512-bit configuration.

Table 2. BMD 512-bit Design File Structure
File Description
BMD_AXIST_512.v Top-level design wrapper
BMD_AXIST_EP_512.v Top-level module
BMD_AXIST_EP_MEM_ACCESS.v Memory access module
BMD_AXIST_EP_MEM.v Memory module
BMD_AXIST_RC_512.v BMD Requester Completion module
BMD_AXIST_CQ_512.v BMD Completer Request module
BMD_AXIST_RQ_512.v BMD Requester Request module
BMD_AXIST_RQ_WRITE_512.v BMD Requester Request write module
BMD_AXIST_RQ_READ_512.v BMD Requester Request read module
BMD_AXIST_RQ_MUX_512.v BMD Requester Write/Read MUX module
BMD_AXIST_CC_512.v BMD Completer Completion module
BMD_AXIST_INTR_CTRL.v Interrupt controller
BMD_AXIST_TO_CTRL.v Turn-off controller module
Note: AMD does not provide drivers for BMD example design.