Assigning GT Locations - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

Unlike in AMD UltraScale+™ and previous devices implementations where direct assignment of GTs are not possible in the user constraints, in Versal Adaptive SoC implementations, the GTs are external to the PCIe IP and hence the GT assignment can be done in user constraints.

Versal Adaptive SoC GT location assignment can be done in the user constraints file, IO planner, or hard block planner. For more information on how to assign GT locations in IO planner or hard block planner, see Synthesizing and Implementing the Design section in Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).

The GT locations are assigned in Quad granularity and not per lane. The lane 0 location and lane ordering are predetermined by whether the GTs are on the left or right side of the device. For details of lane 0 placement and lane ordering, see GT Selection and Pin Planning. Changing the lane 0 location or lane ordering is not supported other than the default setting described in GT Selection and Pin Planning. Following is an example of assigning GTYP locations in a user constraint file.

Note: The gt_quad instances should be assigned contiguously.
set_property LOC GTY_QUAD_X0Y6 [get_cells $gt_quads -filter NAME=~*/gt_quad_3/*]
set_property LOC GTY_QUAD_X0Y5 [get_cells $gt_quads -filter NAME=~*/gt_quad_2/*]
set_property LOC GTY_QUAD_X0Y4 [get_cells $gt_quads -filter NAME=~*/gt_quad_1/*]
set_property LOC GTY_QUAD_X0Y3 [get_cells $gt_quads -filter NAME=~*/gt_quad_0/*]