Configuration Status Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The Configuration Status interface provides information on how the core is configured, such as the negotiated link width and speed, the power state of the core, and configuration errors. The following table defines the ports in the Configuration Status interface of the core.

Table 1. Configuration Status Interface Port Descriptions
Port I/O Width Description
cfg_phy_link_down O 1 Configuration Link Down

Status of the PCI Express link based on the Physical Layer LTSSM.

  • 1b: Link is Down (LinkUp state variable is 0b)
  • 0b: Link is Up (LinkUp state variable is 1b)
Note: Per the PCI Express Base Specification, rev. 3.0, LinkUp is 1b in the Recovery, L0, L0s, L1, and L2 cfg_ltssm states. In the Configuration state, LinkUp can be 0b or 1b. It is always 0b when the Configuration state is reached using Detect > Polling > Configuration. LinkUp is 1b if the configuration state is reached through any other state transition.
Note: While reset is asserted, the output of this signal are 0b until reset is released.
cfg_phy_link_status O 2 Configuration Link Status

Status of the PCI Express link.

  • 00b: No receivers detected
  • 01b: Link training in progress
  • 10b: Link up, DL initialization in progress
  • 11b: Link up, DL initialization completed
cfg_negotiated_width O 3 Negotiated Link Width

This output indicates the negotiated width of the given PCI Express Link and is valid when cfg_phy_link_status[1:0] == 11b (DL Initialization is complete).

Negotiated Link Width values:

  • 000b = x1
  • 001b = x2
  • 010b = x4
  • 011b = x8
  • 100b = x16
  • Other values are reserved.
cfg_current_speed O

2 in PL-PCIE4

3 in PL-PCIE5

Current Link Speed

This signal outputs the current link speed of the given PCI Express Link.

  • 000b: 2.5 GT/s PCI Express Link Speed
  • 001b: 5.0 GT/s PCI Express Link Speed
  • 010b: 8.0 GT/s PCI Express Link Speed
  • 011b: 16.0 GT/s PCI Express Link Speed
  • 100b: 32.0 GT/s PCI Express Link Speed
cfg_max_payload O 2 Max_Payload_Size

This signal outputs the maximum payload size from Device Control register bits 7 down to 5. This field sets the maximum TLP payload size. As a Receiver, the logic must handle TLPs as large as the set value. As a Transmitter, the logic must not generate TLPs exceeding the set value.

  • 00b: 128 bytes maximum payload size
  • 01b: 256 bytes maximum payload size
  • 10b: 512 bytes maximum payload size
  • 11b: 1024 bytes maximum payload size
cfg_max_read_req O 3 Max_Read_Request_Size

This signal outputs the maximum read request size from Device Control register bits 14 down to 12. This field sets the maximum Read Request size for the logic as a Requester. The logic must not generate Read Requests with size exceeding the set value.

  • 000b: 128 bytes maximum Read Request size
  • 001b: 256 bytes maximum Read Request size
  • 010b: 512 bytes maximum Read Request size
  • 011b: 1024 bytes maximum Read Request size
  • 100b: 2048 bytes maximum Read Request size
  • 101b: 4096 bytes maximum Read Request size
  • Other values are reserved
cfg_function_status O

16 in PL-PCIE4

4 in PL-PCIE5

Configuration Function Status

These outputs indicate the states of the Command register bits in the PCI configuration space of each function. These outputs are used to enable requests and completions from the host logic. The assignment of bits is as follows:

  • Bit 0: Function 0 I/O Space Enable
  • Bit 1: Function 0 Memory Space Enable
  • Bit 2: Function 0 Bus Master Enable
  • Bit 3: Function 0 INTx Disable
  • Bit 4: Function 1 I/O Space Enable
  • Bit 5: Function 1 Memory Space Enable
  • Bit 6: Function 1 Bus Master Enable
  • Bit 7: Function 1 INTx Disable
  • Bit 8: Function 2 I/O Space Enable
  • Bit 9: Function 2 Memory Space Enable
  • Bit 10: Function 2 Bus Master Enable
  • Bit 11: Function 2 INTx Disable
  • Bit 12: Function 3 I/O Space Enable
  • Bit 13: Function 3 Memory Space Enable
  • Bit 14: Function 3 Bus Master Enable
  • Bit 15: Function 3 INTx Disable
Note: In PL-PCIE5, only the Function 0 state is indicated. For subsequent functions, the wrreq interface is used.
cfg_vf_status O 504

Configuration Virtual Function Status

  • Bit-0: Virtual function 0: Configured/Enabled by the software.
  • Bit-1: Virtual function 0: PCI Command register, Bus Master Enable.
  • Bit-2: Virtual function 1: Configured/Enabled by software.
  • Bit-3: Virtual function 1: PCI Command register, Bus Master Enable.
cfg_function_power_state O

12 in PL-PCIE4

3 in PL-PCIE5

Configuration Function Power State

These outputs indicate the current power state of the physical functions. Bits [2:0] capture the power state of function 0, and bits [5:3] capture that of function 1, and so on. The possible power states are:

  • 000: D0_uninitialized
  • 001: D0_active
  • 010: D1
  • 100: D3_hot
  • Other values are reserved.
Note: In PL-PCIE5, only the Function 0 state is indicated. For subsequent functions, the wrreq interface is used.
cfg_vf_power_state O 756 Configuration Virtual Function Power State

These outputs indicate the current power state of the virtual functions. Bits [2:0] capture the power state of virtual function 0, and bits [5:3] capture that of virtual function 1, and so on. The possible power states are:

  • 000: D0_uninitialized
  • 001: D0_active
  • 010: D1
  • 100: D3_hot
  • Other values are reserved.
cfg_link_power_state O 2 Current power state of the PCI Express link, and is valid when cfg_phy_link_status[1:0] == 11b (DL Initialization is complete).
  • 00: L0
  • 01: TX L0s
  • 10: L1
  • 11: L2/3 Ready
cfg_local_error_out O 5 Local Error Conditions: Error priority is noted and priority 0 has the highest priority.
  • 00000b - Reserved
  • 00001b - Physical Layer Error Detected (Priority 21)
  • 00010b - Link Replay Timeout (Priority 17)
  • 00011b - Link Replay Rollover (Priority 18)
  • 00100b - Link Bad TLP Received (Priority 15)
  • 00101b - Link Bad DLLP Received (Priority 16)
  • 00110b - Link Protocol Error (Priority 10)
  • 00111b - Replay Buffer RAM Correctable ECC Error (Priority 27)
  • 01000b - Replay Buffer RAM Uncorrectable ECC Error (Priority 4)
  • 01001b - Receive Posted Request RAM Correctable ECC Error (Priority 25)
  • 01010b - Receive Posted Request RAM Uncorrectable ECC Error (Priority 2)
  • 01011b - Receive Completion RAM Correctable ECC Error (Priority 26)
  • 01100b - Receive Completion RAM Uncorrectable ECC Error (Priority 3)
  • 01101b - Receive Posted Buffer Overflow Error (Priority 6)
  • 01110b - Receive Non-Posted Buffer Overflow Error (Priority 7)
  • 01111b - Receive Completion Buffer Overflow Error (Priority 8)
  • 10000b - Flow Control Protocol Error (Priority 9)
  • 10001b - Transmit Parity Error Detected (Priority 5)
  • 10010b - Unexpected Completion Received (Priority 20)
  • 10011b - Completion Timeout Detected (Priority 19)
  • 10100b - AXI4ST RQ INTFC Packet Drop (Priority 22)
  • 10101b - AXI4ST CC INTFC Packet Drop (Priority 23)
  • 10110b - AXI4ST CQ Poisoned Drop (Priority 24)
  • 10111b - axi2cfg_rq_parity_error_detected_i (Priority 1)
  • 11000b - axi2cfg_cc_parity_error_detected_i (Priority 0)
  • 11001b - Reserved
  • 11010b - Reserved
  • 11011b - MSIX RAM Internal Correctable Error (Priority 29)
  • 11100b - MSIX RAM Internal Uncorrectable Error (Priority 13)
  • 11101b - DVSEC RAM Internal Correctable Error (Priority 30)
  • 11110b - DVSEC RAM Internal Uncorrectable Error (Priority 14)
  • 11111b - Reserved
cfg_local_error_valid O 1 Local Error Conditions Valid: Block activates this output for one cycle when any of the errors in cfg_local_error_out[4:0] are encountered. When driven 1b cfg_local_error_out[4:0] indicates local error type. Priority of error reporting (for the case of concurrent errors) is noted.
cfg_rx_pm_state O 2 Current RX Active State Power Management L0s State: Encoding is listed below and valid when cfg_ltssm_state is indicating L0:
  • RX_NOT_IN_L0s = 0
  • RX_L0s_ENTRY = 1
  • RX_L0s_IDLE = 2
  • RX_L0s_FTS = 3
cfg_tx_pm_state O 2 Current TX Active State Power Management L0s State: Encoding is listed below and valid when cfg_ltssm_state is indicating L0:
  • TX_NOT_IN_L0s = 0
  • TX_L0s_ENTRY = 1
  • TX_L0s_IDLE = 2
  • TX_L0s_FTS = 3
cfg_ltssm_state O 6 LTSSM State. Shows the current LTSSM state:
  • 00: Detect.Quiet
  • 01: Detect.Active
  • 02: Polling.Active
  • 03: Polling.Compliance
  • 04: Polling.Configuration
  • 05: Configuration.Linkwidth.Start
  • 06: Configuration.Linkwidth.Accept
  • 07: Configuration.Lanenum.Accept
  • 08: Configuration.Lanenum.Wait
  • 09: Configuration.Complete
  • 0A: Configuration.Idle
  • 0B: Recovery.RcvrLock
  • 0C: Recovery.Speed
  • 0D: Recovery.RcvrCfg
  • 0E: Recovery.Idle
  • 10: L0
  • 11-16: Reserved
  • 17: L1.Entry
  • 18: L1.Idle
  • 19-1A: Reserved
  • 20: Disabled
  • 21: Loopback_Entry_Master
  • 22: Loopback_Active_Master
  • 23: Loopback_Exit_Master
  • 24: Loopback_Entry_Slave
  • 25: Loopback_Active_Slave
  • 26: Loopback_Exit_Slave
  • 27: Hot_Reset
  • 28: Recovery_Equalization_Phase0
  • 29: Recovery_Equalization_Phase1
  • 2a: Recovery_Equalization_Phase2
  • 2b: Recovery_Equalization_Phase3
cfg_rcb_status O

4 in PL-PCIE4

1 in PL-PCIE5

RCB Status.

Provides the setting of the Read Completion Boundary (RCB) bit in the Link Control register of each physical function. In Endpoint mode, bit 0 indicates the RCB for Physical Function 0 (PF 0), bit 1 indicates the RCB for PF 1, and so on. In RC mode, bit 0 indicates the RCB setting of the Link Control register of the RP, bit 1 is reserved.

For each bit, a value of 0 indicates an RCB of 64 bytes and a value of 1 indicates 128 bytes.

Note: In PL-PCIE5, only the Function 0 setting is indicated. For subsequent functions, the wrreq interface is used.
cfg_dpa_substate_change O 4 Dynamic Power Allocation Substate Change.

In Endpoint mode, the core generates a one-cycle pulse on one of these outputs when a Configuration Write transaction writes into the Dynamic Power Allocation Control register to modify the DPA power state of the device. A pulse on bit 0 indicates such a DPA event for PF0 and a pulse on bit 1 indicates the same for PF1. The other 2 bits are reserved.These outputs are not active in Root Port mode.

cfg_obff_enable O 2 Optimized Buffer Flush Fill Enable.

This output reflects the setting of the OBFF Enable field in the Device Control 2 register.

  • 00: OBFF disabled.
  • 01: OBFF enabled using message signaling, Variation A.
  • 10: OBFF enabled using message signaling, Variation B.
  • 11: OBFF enabled using WAKE# signaling.
cfg_pl_status_change O 1 This output is used by the core in Root Port mode to signal one of the following link training-related events:
  • The link bandwidth changed as a result of the change in the link width or operating speed and the change was initiated locally (not by the link partner), without the link going down. This interrupt is enabled by the Link Bandwidth Management Interrupt Enable bit in the Link Control register. The status of this interrupt can be read from the Link Bandwidth Management Status bit of the Link Status register; or
  • The link bandwidth changed autonomously as a result of the change in the link width or operating speed and the change was initiated by the remote node. This interrupt is enabled by the Link Autonomous Bandwidth Interrupt Enable bit in the Link Control register. The status of this interrupt can be read from the Link Autonomous Bandwidth Status bit of the Link Status register; or
  • The Link Equalization Request bit in the Link Status 2 register was set by the hardware because it received a link equalization request from the remote node. This interrupt is enabled by the Link Equalization Interrupt Enable bit in the Link Control 3 register. The status of this interrupt can be read from the Link Equalization Request bit of the Link Status 2 register.

The pl_interrupt output is not active when the core is configured as an Endpoint.

cfg_ext_tag_enable O 1 Extended Tag Enable:Per function state of Device Control Register Ext Tag (8-Bit) Enable bit.
cfg_atomic_requester_enable O

4 in PL-PCIE4

1 in PL-PCIE5

Atomic Operation Requester Enable: Per function state of Device Control2 Register AtomicOp Requester Enable bit.
Note: In PL-PCIE5, only the Function 0 state is indicated. For subsequent functions, the wrreq interface is used.
cfg_10b_tag_requester_enable O

4 in PL-PCIE4

1 in PL-PCIE5

10b Tag Requester Enable: Per function state of Device Control2 Register 10-Bit Tag Requester Enable bit.
Note: In PL-PCIE5, only the Function 0 state is indicated. For subsequent functions, the wrreq interface is used.
pcie_tfc_nph_av O 4 This output provides an indication of the currently available header credit for Non-Posted TLPs on the transmit side of the core. The user logic can check this output before transmitting a Non-Posted request on the requester request interface, to avoid blocking the interface when no credit is available. The encodings are:
  • 0000: No credit available
  • 0001: 1 credit available
  • 0010: 2 credits available
  • ...
  • 1110: 14 credits available
  • 1111: 15 or more credits available

Because of pipeline delays, the value on this output can not include the credit consumed by the Non-Posted requests in the last eight cycles or less. The user logic must adjust the value on this output by the credit consumed by the Non-Posted requests it sent in the previous clock cycles, if any.

pcie_tfc_npd_av O 4 This output provides an indication of the currently available payload credit for Non-Posted TLPs on the transmit side of the core. The user logic checks this output before transmitting a Non-Posted request on the requester request interface, to avoid blocking the interface when no credit is available. The encodings are:
  • 0000: No credit available
  • 0001: 1 credit available
  • 0010: 2 credits available
  • ...
  • 1110: 14 or more credits available
  • 1111: 15 or more credits available

Because of pipeline delays, the value on this output does not include the credit consumed by the Non-Posted requests sent by the user logic in the last eight clock cycles or less. The user logic must adjust the value on this output by the credit consumed by the Non-Posted requests it sent in the previous clock cycles, if any.

pcie_rq_tag_av O 4 This output provides an indication of the number of free tags available for allocation to Non-Posted requests on the PCIe master side of the core. The user logic checks this output before transmitting a Non-Posted request on the requester request interface, to avoid blocking the interface when no tags are available. The encodings are:
  • 0000: No tags available
  • 0001: 1 tag available
  • 0010: 2 tags available
  • ...
  • 1110: 14 tags available
  • 1111: 15 or more tags available

Because of pipeline delays, the value on this output does not include the tags consumed by the Non-Posted requests sent by the user logic in the last 8 clock cycles or less. The user logic must adjust the value on this output by the number of Non-Posted requests it sent in the previous clock cycles, if any.