Supported Clock Frequencies and Interface Widths - 1.0 English - PG343

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
Document ID
PG343
Release Date
2024-11-22
Version
1.0 English
Table 1. Clock Frequencies and Interface Widths Supported For Various Configurations
PCIe Link Speed Capability PCIe Link Width Capability PIPE Interface Data Widths (bits) AXI4 Streaming Interface Data Width (bits) pipe_clk Frequency (MHz) core_clk Frequency (MHz) user_clk2 Frequency (MHz) (axi4st) user_clk Frequency (MHz) (cfg, axi4st)
Gen1 X1 16 64 125 250 62.5 62.5
16 64 125 250 125 125
16 64 125 250 250 250
X2 16 64 125 250 62.5 62.5
16 64 125 250 125 125
16 64 125 250 250 250
X4 16 64 125 250 125 125
16 64 125 250 250 250
X8 16 64 125 250 250 250
16 128 125 250 125 125
X16 16 128 125 250 250 250
Gen2 X1

16/16

 64 125/250 250 62.5 62.5

16/16

 64 125/250 250 125 125

16/16

 64 125/250 250 250 250
X2

16/16

 64 125/250 250 125 125

16/16

 64 125/250 250 250 250
X4

16/16

 64 125/250 250 250 250

16/16

 128 125/250 250 125 125
X8

16/16

 128 125/250 250 250 250

16/16

 256 125/250 250 125 125
X16

16/16

 256 125/250 250 250 250
Gen3 X1

16/16/32

 64

125/250/250

500

 125 125

16/16/32

 64

125/250/250

500

 250 250
X2

16/16/32

 64

125/250/250

500

 250 250

16/16/32

 128

125/250/250

500

 125 125
X4

16/16/32

 128

125/250/250

500

 250 250

16/16/32

 256

125/250/250

500

 125 125
X8

16/16/32

 256

125/250/250

500

 250 250
X16

16/16/32

 512

125/250/250

500 500 250
Gen4 X1

16/16/32/32

64

125/250/250/500

500

 250 250

16/16/32/32

128

125/250/250/500

500

 125 125
X2

16/16/32/32

128

125/250/250/500

500

 250 250

16/16/32/32

256

125/250/250/500

500

 125 125
X4

16/16/32/32

256

125/250/250/500

500

 250 250
X8

16/16/32/32

512

125/250/250/500

500 500 250
Gen5 X1 16/16/32/32/64 128 125/250/250/500 500 500 250
X2 16/16/32/32/64 256 125/250/250/500 500 500 250
X4 16/16/32/32/64 512 125/250/250/500 500 500 250
  1. For Gen1/Gen2 speed, the pipe data width is 16. For Gen3 speed, the pipe data width is 32 and for Gen4 speed, it is 64. In Gen3 configuration, when in Gen1, the pipe data width switches to 16. Similarly, the automatic switch happens in Gen4 based on the speed during the link training process. The pipe data width is not user configurable.