Endpoint Configuration - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The simulation environment provided with the Versal™ Adaptive SoC Integrated Block for PCI Express® core in Endpoint configuration performs simple memory access tests on the PIO example design. Transactions are generated by the Root Port Model and responded to by the PIO example design.

  • PCI Express Transaction Layer Packets (TLPs) are generated by the test bench transmit user application (pci_exp_usrapp_tx). As it transmits TLPs, it also generates a log file, tx.dat.
  • PCI Express TLPs are received by the test bench receive user application (pci_exp_usrapp_rx). As the user application receives the TLPs, it generates a log file, rx.dat.

    For more information about the test bench, see Root Port Model Test Bench for Endpoint in the next chapter.