Straddle Option on RC Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The RC interface supports a straddle option that allows up to four TLPs to be transferred over the interface in the same beat. This option can be enabled during core configuration in the AMD Vivado™ IDE. When enabled, the core might start a new Completion TLP on byte lanes 0, 16, 32, or 48. Thus, with this option enabled, it is possible for the core to send four Completion TLPs entirely in the same beat on the AXI bus, if each of them has a payload of size one Dword or less. The straddle option can only be used when the RC interface is configured in the Dword-aligned mode.

When the Requester Completion (RC) interface is configured for a width of 256 or 512 bits, depending on the type of TLP and Payload size, there can be significant interface use inefficiencies, if a maximum of 1 TLP for 256 bits or 2 TLPs for 512 bits is allowed to start or end per interface beat. This inefficient use of RC interface can lead to overflow of the completion FIFO when Infinite Receiver Credits are advertized. You must either:

  • Restrict the number of outstanding Non Posted requests, so as to keep the total number of completions received less than 64 and within the completion of the FIFO size selected. The FIFO size is set to 32 KB when you have Gen3X16 -2LV Speed Grade device and size is set to 64 KB for all other devices or configurations, or
  • Use the RC interface straddle option. See the waveform figures for 256 bits (Figure 1) and 512 bits (Figure 1), respectively showing this option.

The straddle option, available only on the 256-bit or 512-bit wide RC interface, is enabled through the Vivado IP Core catalog. See Design Flow Steps for instructions on enabling the option in the IP catalog. When this option is enabled, the integrated block can start a new Completion TLP on byte lane 16/32/48 when the previous TLP has ended at or before byte lane 15/31/47 in the same beat. Thus, with this option enabled, it is possible for the integrated block to send multiple Completion TLPs entirely in the same beat on the RC interface, if neither of them has more than one Dword of payload.

The straddle setting is only available when the interface width is set to 256 bits or 512 bits, and the RC interface is set to Dword-aligned mode.

The following table lists the valid combinations of interface width, addressing mode, and the straddle option.

Table 1. Valid Combinations of Interface Width, Alignment Mode, and Straddle
Interface Width Alignment Mode Straddle Option Description
64 bits Dword-aligned Not applicable 64-bit, Dword-aligned
64 bits Address-aligned Not applicable 64-bit, Address-aligned
128 bits Dword-aligned Not applicable 128-bit, Dword-aligned
128 bits Address-aligned Not applicable 128-bit, Address-aligned
256 bits Dword-aligned Disabled 256-bit, Dword-aligned, straddle disabled
256 bits Dword-aligned Enabled 256-bit, Dword-aligned, straddle enabled (only allowed for the Requester Completion interface)
256 bits Address-aligned Not applicable 256-bit, Address-aligned
512 bits Dword-aligned Disabled 512-bit, Dword-aligned, straddle disabled
512 bits Dword-aligned Enabled 512-bit, Dword-aligned, straddle enabled (2-TLP straddle allowed for all interfaces, 4-TLP straddle only allowed for the Requester Completion interface)
512 bits Address-aligned Not applicable 512-bit, 128-bit Address-aligned