Generating GT and PHY IP - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
Document ID
PG343
Release Date
2024-11-22
Version
1.0 English
GT Wizards and PHY IP are outside of PCIe core instead of under PCIe hierarchy like in UltraScale+ devices. There are two ways to generate the two cores according to your PCIe core configuration:

Run Block Automation in IP Integrator

To run block automation:

  1. In the Flow Navigator, select Create Block Design.

  2. Add the pcie_versal IP to your block design.
  3. Configure the pcie_versal core by double-clicking on pcie_versal block in your block design (BD).
  4. Click Run Block Automation, and click OK.

The PHY IP and GT quads are found in the generated Vivado IP integrator design, pcie_versal_0_support, along with the helper blocks for reset and clock, as seen in the following figure. For more details, see Example Design.

GT Quad locations can only be set using user constraints in the Xilinx Design Constraints (XDC) file. For more information, see GT Locations.