Requester Memory Write Operation - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

In both Dword-aligned and 128-bit address aligned modes, the transfer starts with the sixteen descriptor bytes, followed by the payload bytes. The user application must keep the signal s_axis_rq_tvalid asserted over the duration of the packet. The core treats the deassertion of s_axis_rq_tvalid during the packet transfer as an error, and nullifies the corresponding request TLP transmitted on the link to avoid data corruption.

The user application must also assert the signal s_axis_rq_tlast in the last beat of the packet. The core are by pull down s_axis_rq_tready in any cycle if it is not ready to accept data. The user application must not change the values on s_axis_rq_tdata and s_axis_rq_tlast during the transfer when the core has deasserted s_axis_rq_tready. The AXI4-Stream interface signals m_axis_rq_tkeep (one per Dword position) must be set to indicate the valid Dwords in the packet including the descriptor and any null bytes inserted between the descriptor and the payload. That is, the m_axis_rq_tkeep bits must be set to 1 contiguously from the first Dword of the descriptor until the last Dword of the payload. During the transfer of a packet, the m_axis_rq_tkeep bits can be 0 only in the last beat of the packet, when the packet does not fill the entire width of the interface.

The requester request interface also includes the First Byte Enable and the Last Enable bits in the s_axis_rq_tuser bus. These must be set in the first beat of the packet, and provides information of the valid bytes in the first and last Dwords of the payload.

The user application must limit the size of the payload transferred in a single request to the maximum payload size configured in the core, and must ensure that the payload does not cross a 4 Kbyte boundary. For memory writes of two Dwords or less, the 1s in first_be[7:0] and last_be[7:0] are not be contiguous. For the special case of a zero-length memory write request, the user application must provide a dummy one_dword payload with first_be[7:0] and last_be[7:0] both set to all 0s. In all other cases, the 1 bits in first_be[7:0] and last_be[7:0] must be contiguous. In Straddled case, addr_offset[3:2], first_be[7:4], and last_be[7:4] are used to indicate second TLP information while addr_offset[1:0], first_be[3:0], and last_be[3:0] are used to indicate the first TLP information on that data beat.

The following figure illustrates the Dword-aligned transfer of a memory write request from the user logic across the requester request interface. For the purpose of illustration, the size of the data block being written into user memory is assumed to be n Dwords, for some n = k*16 - 1, where k > 1 .

Figure 1. Memory Write Transaction on the Requester Request Interface (Dword-Aligned Mode)

The following figure illustrates the 128-bit address aligned transfer of a memory write request from the user application across the requester request interface. For the purpose of illustration, the starting Dword offset of the data block is assumed to be (m*16 +3), for some integer m > 0. Its size is assumed to be n Dwords, for some n = k*16 -1, k > 1. In the 128-bit address-aligned mode, the delivery of the payload always starts in the second 128-bit quarter of the 512-bit word, following the descriptor in the first quarter. The user application must communicate the offset of the first Dword of the payload in the addr_offset[3:0] field of the s_axis_rq_tuser bus. The user application must also set the bits in first_be[7:0] to indicate the valid bytes in the first Dword and the bits in last_be[7:0] to indicate the valid bytes in the last Dword of the payload.

Figure 2. Memory Write Transaction on the Requester Request Interface (128-bit Address Aligned Mode)