Completer Model - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The Completer Model is enabled through the Vivado Tcl Console by executing the following command after a core has been configured:

set_property-dict [list CONFIG.completer_model {true}] [get_ips <PCIe IP Core Name>]

When the core is configured with the 512-bit AXI Interface, you can opt in for this Completer Model test bench which can be used with your design to exercise bus-mastering functionality (upstream direction traffic from the Endpoint DUT to the Root Port Model).

The Completer Model provides a Root Port side memory array (DATA_STORE_2) that can be written through a Memory Write transaction and be read through a Memory Read transaction from the Endpoint DUT. This memory can be configured through two different parameters available at the top level of the Root Port Model module (xilinx_pcie_uscale_rp.v).

RP_BAR[63:0]
Provides the address of the first byte of the DATA_STORE_2 array.
RP_BAR_SIZE[5:0]
Provides the number of byte address bits -1 of the DATA_STORE_2 array. For example, a value of 11 provides 2^(11+1) bytes or 4 KB of available memory.

Each memory transaction is checked against the memory array location based on the two aforementioned parameters, byte enables, 4K boundaries, Max Payload Size, and Max Read Request Size rules set at the Root Port model. Each Memory Read Completion returned is split according to Max Payload Size and Read Completion Boundary rules. The Completer Model also supports a Zero Length Write packet which intercepts the packet but does not store its payload data, and a Zero Length Read packet which returns a one DW payload data.