Straddle Option on CQ Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The core has the capability to start the transfer of a new request on the requester completion interface in the same beat when the previous request has ended on or before Dword position 7 on the data bus. This straddle option is enabled during core customization in the AMD Vivado™ IDE. The straddle option can be used only with the Dword-aligned mode.

When the straddle option is enabled, request TLPs are transferred on the AXI4-Stream interface as a continuous stream, with no packet boundaries. Thus, the signals m_axis_cq_tkeep and m_axis_cq_tlast are not useful in determining the boundaries of TLPs delivered on the interface (the core sets m_axis_cq_tkeep to all 1s and m_axis_cq_tlast to 0 permanently when the straddle option is in use.). Instead, delineation of TLPs is performed using the following signals provided within the m_axis_cq_tuser bus.

  • is_sop[0]: The core sets this output to active-High in a beat when there is at least one request TLP starting in the beat. The position of the first byte of the descriptor of this TLP is determined as follows:
    • If the previous TLP ended before this beat, the first byte of the descriptor is in byte lane 0.
    • If a previous TLP is continuing in this beat, the first byte of this descriptor is in byte lane 32. This is possible only when the previous TLP ends in the current beat, that is when is_eop[0] is also set.
  • is_sop[1]: The core asserts this output in a beat when there are two request TLPs starting in the same beat. The first TLP always starts at byte position 0 and the second TLP at byte position 32. The core starts a second TLP at byte position 32 only if the previous TLP ended before byte position 32 in the same beat, that is only if is_eop[0] is also set in the same beat.
  • is_eop[0]: This output is used to indicate the end of a request TLP. Its assertion signals that there is at least one TLP ending in this beat.
  • is_eop0_ptr[3:0]: When is_eop[0] is asserted, is_eop0_ptr[3:0] provides the offset of the last Dword of the corresponding TLP ending in this beat. For TLPs with a payload, the offset for the last byte can be also be determined from the starting address and length of the TLP, or from the byte enable signals byte_en[63:0].
  • is_eop[1]: This output is used to indicate that there are two TLPs ending in a beat. Its assertion signals that there is at least one TLP ending in this beat. is_eop[1] can be set only when is_eop[0] is also set.
  • is_eop1_ptr[3:0]: When is_eop[1] is asserted, is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP ending in this beat. For TLPs with a payload, the offset for the last byte can be also be determined from the starting address and length of the TLP, or from the byte enable signals byte_en[63:0]. Because the second TLP can start only on byte lane 32, it can only end at a byte lane in the range 47-63. Thus the offset is_eop1_ptr[3:0] can only take a value in the range 11-15.
Figure 1. Transfer of Request TLPs on the Completer Request Interface with the Straddle Option Enabled

The previous figure illustrates the transfer of four request TLPs on the completer request interface when the straddle option is enabled. For all TLPs, the first Dword of the payload always follows the descriptor without any gaps. The first request TLP (REQ 1) starts at Dword position 0 of Beat 1 and ends in Dword position 5 of Beat 3. The second TLP (REQ 2) starts in Dword position 8 of the same beat. This second TLP has only a four-Dword payload, so it also ends in the same beat. The third and fourth request TLPs are transferred completely in Beat 4, as REQ 3 has only a one-Dword payload and REQ 4 has no payload.