Completer Request Descriptor Formats - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The core transfers each request TLP received from the link over the completer request interface as an independent AXI4-Stream packet. Each packet starts with a descriptor, and can have payload data following the descriptor. The descriptor is always 16 bytes long, and is sent in the first 16 bytes of the request packet. The descriptor is always transferred during the first beat on the 512-bit interface. The formats of the descriptor for different request types are illustrated in the following figures.

The format of the following figure applies when the request TLP being transferred is a memory read/write request, an I/O read/write request, or an Atomic Operation request.

Figure 1. Completer Request Descriptor Format for Memory, I/O, and Atomic Op Requests
Figure 2. Completer Request Descriptor Format for Configuration Requests

The format of the following figure is used for Vendor-Defined Messages (Type 0 or Type 1) only.

Figure 3. Completer Request Descriptor Format for Vendor-Defined Messages

The format of the following figure is used for all ATS messages (Invalid Request, Invalid Completion, Page Request, PRG Response).

Figure 4. Completer Request Descriptor Format for ATS Messages

For all other messages, the descriptor takes the format of the following figure.

Figure 5. Completer Request Descriptor Format for All Other Messages

The following tables describe the individual fields of the completer request descriptor.

Table 1. Completer Request Descriptor Fields for Memory, I/O, and Atomic Operation Requests
Bit Index Field Name Description
1:0 Address Type

This field is defined for memory transactions and Atomic Operations only. It contains the AT bits extracted from the TL header of the request.

  • 00: Address in the request is untranslated
  • 01: Transaction is a Translation Request
  • 10: Address in the request is a translated address
  • 11: Reserved
63:2 Address

This field applies to memory, I/O, and atomic operation requests. It provides the address from the TLP header. This is the address of the first Dword referenced by the request. The First_BE bits from m_axis_cq_tuser must be used to determine the byte-level address.

When the transaction specifies a 32-bit address, bits [63:32] of this field are 0.

74:64 Dword Count These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). Its range is 0 - 1024 Dwords. For I/O accesses, the Dword count is always 1. For memory read requests Dword count is in the range 1 - 1024. For a zero length memory read/write request, the Dword count is 1, with the First_BE bits set to all zeroes.
78:75 Request Type Identifies the transaction type. The transaction types and their encodings are listed in Table 6.
79 Poisoned Request / T8 When 10b Tag Completer is enabled, for Non-Posted transactions, this bit is to carry PCIe Tag[8]. Otherwise, when CQ poisoned packet handling is set to not discard (via AXISTEN_IF_CQ_POISON_DISCARD_DISABLE attribute) for transactions with payload, this bit is used to indicate poisoned request. This bit is reserved in all other cases.
95:80 Requester ID PCI Requester ID associated with the request. With the legacy interpretation of RIDs, these 16 bits are divided into an 8-bit bus number [95:88], 5- bit device number [87:83], and 3-bit Function number [82:80]. When ARI is enabled, bits [95:88] carry the 8-bit bus number and [87:80] provide the function number. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
103:96 Tag PCIe Tag associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data. This field can be ignored for memory writes and messages
111:104

Target Function

or

Function ID[7:0]

This field is defined for memory, I/O and Atomic Op requests only. It provides the Function number the request is targeted at, determined by the BAR check. When ARI is in use, all 8 bits of this field are valid. Otherwise, only bits [106:104] are valid. Following are Target Function Value to PF/VF map mappings:

  • 0: PF0
  • 1: PF1
  • 2: PF2
  • 3: PF3
  • 4: VF0
  • 5: VF1
  • 6: VF2
  • 7: VF3

For endpoint configuration, this field presents the Function ID[7:0].

114:112 BAR ID

This field is defined for memory, I/O and Atomic Op requests only. It provides the matching BAR number for the address in the request.

000 = BAR 0 (VF-BAR 0 for VFs) 001 = BAR 1 (VF-BAR 1 for VFs) 010 = BAR 2 (VF-BAR 2 for VFs) 011 = BAR 3 (VF-BAR 3 for VFs) 100 = BAR 4 (VF-BAR 4 for VFs) 101 = BAR 5 (VF-BAR 5 for VFs) 110 = Expansion ROM Access For 64-bit transactions, the BAR number is given as the lower address of the matching pair of BARs (that is, 0, 2, or 4).

120:115 (PL-PCIE4) BAR Aperture

This 6-bit field is defined for memory, I/O, and atomic operation requests only.

It provides the aperture setting of the BAR matching the request. This information is useful in determining the bits to be used in addressing its memory or I/O space. For example, a value of 12 indicates that the aperture of the matching BAR is 4K, and the user application can therefore ignore bits [63:12] of the address.

For VF BARs, the value provided on this output is based on the memory space consumed by a single VF covered by the BAR.

119:115 (PL-PCIE5) Function ID[12:8] This 5-bit field is defined for memory, I/O and atomic operation requests and as an endpoint only. It provides upper 5 bits of the Function ID. This field is reserved for configurations other than endpoint.
120 (PL-PCIE5) Reserved Reserved.
123:121 Transaction Class (TC) PCIe transaction class (TC) associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
126:124 Attributes

These bits provide the setting of the attribute bits associated with the request. Bit 124 is the No Snoop bit and bit-125 is the relaxed ordering bit. Bit 126 is the ID-Based ordering bit, and can be set only for memory requests and messages.

When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.

127 T9 When 10b Tag Completer is enabled, for Non-Posted transactions, this bit is to carry PCIe Tag[9]. This bit is reserved in all other cases.
Table 2. Completer Request Descriptor Fields for Configuration Requests
Bit Index Field Name Description
1:0 Reserved Reserved field as all the config accesses are DWORD based addresses.
7:2 Reg Number DWORD based Register Number for the config space.
11:8 Extended Reg Number Register addresses beyond FFh addresses.
63:12 Reserved Reserved field
74:64 Dword Count These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). Its range is 0 - 1024 Dwords. For I/O accesses, the Dword count is always 1. For memory read requests Dword count is in the range 1 - 1024. For a zero length memory read/write request, the Dword count is always 1, with the First_BE bits set to all zeroes.
78:75 Request Type Identifies the transaction type. The transaction types and their encodings are listed in Table 6.
79 Poisoned Request / T8 When 10b Tag Completer is enabled, for Non-Posted transactions, this bit is to carry PCIe Tag[8]. Otherwise, when CQ poisoned packet handling is set to not discard (via AXISTEN_IF_CQ_POISON_DISCARD_DISABLE attribute) for transactions with payload, this bit is used to indicate poisoned request. This bit is reserved in all other cases.
95:80

Requester ID

or

Function ID [12:0] with the upper 3 bits reserved

PCI Requester ID associated with the request. With the legacy interpretation of RIDs, these 16 bits are divided into an 8-bit bus number [95:88], 5- bit device number [87:83], and 3-bit Function number [82:80]. When ARI is enabled, bits [95:88] carry the 8-bit bus number and [87:80] provide the Function number. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
103:96 Tag PCIe Tag associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data. This field can be ignored for memory writes and messages.
119:104

Target Function

or

Function ID[7:0]

This field is applicable only to Configuration requests and messages routed by ID. For these requests, this field specifies the PCI Completer ID associated with the request (these 16 bits are divided into an 8-bit bus number, 5-bit device number, and 3-bit function number in the legacy interpretation mode. In the ARI mode, these 16 bits are treated as an 8-bit bus number + 8-bit Function number.).
120 Reserved Reserved.

123:121

Transaction Class (TC) PCIe Transaction Class (TC) associated with the request.
126:124 Attributes

These bits provide the setting of the Attribute bits associated with the request. Bit 124 is the No Snoop bit and bit 125 is the Relaxed Ordering bit. Bit 126 is the ID-Based Ordering bit, and can be set only for memory requests and messages.

The core forces the attribute bits to 0 in the request sent on the link if the corresponding attribute is not enabled in the Function’s PCI Express Device Control Register.

127 T9 When 10-bit tags are enabled for the requester, this field is used to transport bit [9] of the PCIe tag associated with Non-Posted requests. This field must be set to 0 when sending a Posted request.
Table 3. Completer Request Descriptor Fields for Vendor-Defined Messages
Bit Index Field Name Description
15:0 Destination ID This field applies to vendor-defined messages only. When the message is routed by ID (that is, when the message routing field is 010 binary), this field provides the Destination ID of the message.
31:16 Vendor ID This field applies to vendor-defined messages only. It provides the Vendor ID for the message.
63:32 Vendor-Defined Header This field applies to vendor-defined messages only. It contains the bytes extracted from Dword 3 of the TL header.
74:64 Dword Count These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). Its range is 0 - 1024 Dwords. For I/O accesses, the Dword count is always 1. For memory read requests Dword count is in the range 1 - 1024. For a zero length memory read/write request, the Dword count is 1, with the First_BE bits set to all zeroes.
78:75 Request Type Identifies the transaction type. The transaction types and their encodings are listed in Table 6.
79 Poisoned Request / T8 When 10b tag completer is enabled, for Non-Posted transactions, this bit is to carry PCIe Tag[8]. Otherwise, when CQ poisoned packet handling is set to not discard (via AXISTEN_IF_CQ_POISON_DISCARD_DISABLE attribute) for transactions with payload, this bit is used to indicate poisoned request. This bit is reserved in all other cases.
95:80 Requester ID PCI Requester ID associated with the request. With the legacy interpretation of RIDs, these 16 bits are divided into an 8-bit bus number [95:88], 5- bit device number [87:83], and 3-bit Function number [82:80]. When ARI is enabled, bits [95:88] carry the 8-bit bus number and [87:80] provide the Function number. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
103:96 Tag PCIe Tag associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data. This field can be ignored for memory writes and messages
111:104 Message Code This field is defined for all messages. It contains the 8-bit Message Code extracted from the TL header.
114:112 Message Routing This field is defined for all messages. These bits provide the 3-bit Routing field r[2:0] from the TL header.
120:115 Reserved Reserved.
123:121 Transaction Class (TC) PCIe Transaction Class (TC) associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
126:124 Attributes

These bits provide the setting of the attribute bits associated with the request. Bit-124 is the No-Snoop bit and bit-125 is the Relaxed Ordering bit. Bit-126 is the ID-Based Ordering bit, and it can be set only for memory requests and messages.

When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.

127 T9 When 10b Tag Completer is enabled, for Non-Posted transactions, this bit is to carry PCIe Tag[9]. This bit is reserved in all other cases.
Table 4. Completer Request Descriptor Fields for ATS Messages
Bit Index Field Name Description
63:0 ATS Header This field is applicable to ATS messages only. It contains the bytes extracted from Dwords 2 and 3 of the TL header.
74:64 Dword Count These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). Its range is 0 - 1024 Dwords. For I/O accesses, the Dword count is always 1. For memory read requests Dword count is in the range 1 - 1024. For a zero length memory read/write request, the Dword count is 1, with the First_BE bits set to all zeroes.
78:75 Request Type

Identifies the transaction type. The transaction types and their encodings are listed in Table 6.

79 Poisoned Request / T8 When 10b Tag Completer is enabled, for Non-Posted transactions, this bit is to carry PCIe Tag[8]. Otherwise, when CQ Poisoned Packet handling is set to not discard (via AXISTEN_IF_CQ_POISON_DISCARD_DISABLE attribute) for transactions with payload, this bit is used to indicate poisoned request. This bit is reserved in all other cases.
95:80 Requester ID PCI Requester ID associated with the request. With the legacy interpretation of RIDs, these 16 bits are divided into an 8-bit bus number [95:88], 5-bit device number [87:83], and 3-bit Function number [82:80]. When ARI is enabled, bits [95:88] carry the 8-bit bus number and [87:80] provide the function number. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
103:96 Tag PCIe tag associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data. This field can be ignored for memory writes and messages.
111:104 Message Code This field is defined for all messages. It contains the 8-bit message code extracted from the TL header.
114:112 Message Routing This field is defined for all messages. These bits provide the 3-bit routing field r[2:0] from the TL header.
120:115 Reserved Reserved.
123:121 Transaction Class (TC) PCIe transaction class (TC) associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
126:124 Attributes

These bits provide the setting of the attribute bits associated with the request. Bit-124 is the No-Snoop bit and bit-125 is the Relaxed Ordering bit. Bit-126 is the ID-Based Ordering bit, and it can be set only for memory requests and messages.

When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.

127 T9 When 10b Tag Completer is enabled, for Non-Posted transactions, this bit is to carry PCIe Tag[9]. This bit is reserved in all other cases.
Table 5. Completer Request Descriptor Fields for all Other Messages
Bit Index Field Name Description
15:0 Snoop Latency This field is defined for LTR messages only, it is reserved for the others. It provides the value of the 16-bit Snoop Latency field in the TL header of the message.
31:16 No-Snoop Latency This field is defined for LTR messages only, it is reserved for the others. It provides the value of the 16-bit No-Snoop Latency field in the TL header of the message.
35:32 OBFF Code

This field is defined for OBFF messages only, it is reserved for the others. The OBFF Code field is used to distinguish between various OBFF cases:

  • 1111b : "CPU Active" – System fully active for all device actions including bus mastering and interrupts
  • 0001b : "OBFF" – System memory path available for device memory read/write bus master activities
  • 0001b : "OBFF" – System memory path available for device memory read/write bus master activities
  • 0001b : "OBFF" – System memory path available for device memory read/write bus master activities
  • 0000b "Idle" – System in an idle, low power state
  • 0000b "Idle" – System in an idle, low power state
  • All other codes are reserved.
63:36 Reserved Reserved
74:64 Dword Count These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). Its range is 0 - 1024 Dwords. For I/O accesses, the Dword count is always 1. For memory read requests Dword count is in the range 1 - 1024. For a zero length memory read/write request, the Dword count is 1, with the First_BE bits set to all zeroes.
78:75 Request Type Identifies the transaction type. The transaction types and their encodings are listed in Table 6.
79 Poisoned Request / T8 When 10b tag completer is enabled for Non-Posted transactions, this bit is to carry PCIe Tag[8]. Otherwise, when CQ poisoned packet handling is set to not discard (via AXISTEN_IF_CQ_POISON_DISCARD_DISABLE attribute) for transactions with payload, this bit is used to indicate poisoned request. This bit is reserved in all other cases.
95:80 Requester ID PCI Requester ID associated with the request. With the legacy interpretation of RIDs, these 16 bits are divided into an 8-bit bus number [95:88], 5- bit device number [87:83], and 3-bit Function number [82:80]. When ARI is enabled, bits [95:88] carry the 8-bit bus number and [87:80] provide the Function number. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
103:96 Tag PCIe tag associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data. This field can be ignored for memory writes and messages
111:104 Message Code This field is defined for all messages. It contains the 8-bit Message Code extracted from the TL header.
114:112 Message Routing This field is defined for all messages. These bits provide the 3-bit Routing field r[2:0] from the TL header.
120:115 Reserved Reserved.
123:121 Transaction Class (TC) PCIe transaction class (TC) associated with the request. When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.
126:124 Attributes

These bits provide the setting of the Attribute bits associated with the request. Bit-124 is the No-Snoop bit and bit-125 is the Relaxed Ordering bit. Bit-126 is the ID-Based Ordering bit, and can be set only for memory requests and messages.

When the request is a Non-Posted transaction, the client completer application must store this field and supply it back to the core with the completion data.

127 T9 When 10b Tag Completer is enabled for Non-Posted transactions, this bit is to carry PCIe Tag[9]. This bit is reserved in all other cases.
Table 6. Transaction Types
Request Type (binary) Description
0000 Memory Read Request
0001 Memory Write Request
0010 I/O Read Request
0011 I/O Write Request
0100 Memory Fetch and Add Request
0101 Memory Unconditional Swap Request
0110 Memory Compare and Swap Request
0111 Locked Read Request (allowed only in Legacy Devices)
1000 Type 0 Configuration Read Request (on Requester side only)
1001 Type 1 Configuration Read Request (on Requester side only)
1010 Type 0 Configuration Write Request (on Requester side only)
1011 Type 1 Configuration Write Request (on Requester side only)
1100 Any message, except ATS and Vendor-Defined Messages
1101 Vendor-Defined Message
1110 ATS Message
1111 Reserved