Test Setup Tasks - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. Test Setup Tasks
Name Input(s) Description
TSK_SYSTEM_INITIALIZATION None

Waits for transaction interface reset and link-up between the Root Port Model and the Endpoint DUT.

This task must be invoked prior to the Endpoint core initialization.

TSK_USR_DATA_SETUP_SEQ None Initializes global 4096 byte DATA_STORE array and resizable DATA_STORE_2 array entries to sequential values from zero to 4095.
TSK_TX_CLK_EAT clock count 31:30 Waits clock_count transaction interface clocks.
TSK_SIMULATION_TIMEOUT timeout 31:0 Sets master simulation timeout value in units of transaction interface clocks. This task should be used to ensure that all DUT tests complete.