New Ports - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. New Ports in the Versal PL PCIe Core
Name I/O Notes
cfg_ext_tag_enable O For details, see Table 1.
cfg_atomic_requester_enable O
cfg_10b_tag_requester_enable O
cfg_fc_ph_scale O For details, see Table 1.
cfg_fc_pd_scale O
cfg_fc_nph_scale O
cfg_fc_npd_scale O
cfg_fc_cplh_scale O
cfg_fc_cpld_scale O
cfg_pasid_enable O For details, see Table 1.
cfg_pasid_exec_permission_enable O
cfg_pasid_privil_mode_enable O
apb3_* For details, see Table 1.
cfg_wrreq_flr_vld O

Configuration Write Request FLR Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the FLR bit field is received from the PCI Express link.
cfg_wrreq_msi_vld O

Configuration Write Request MSI Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the MSI bit field is received from the PCI Express link.
cfg_wrreq_msix_vld O

Configuration Write Request MSIX Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the MSIX bit field is received from the PCI Express link.
cfg_wrreq_bme_vld O

Configuration Write Request BME / Interrupt Disable Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to either the BME bit field or the Interrupt Disable bit field is received from the PCI Express link.
cfg_wrreq_vfe_vld O

Configuration Write Request VFE Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the VF Enable bit field is received from the PCI Express link.
cfg_wrreq_func_num[15:0] O

Configuration Write Request Function Number:

Shows the Function ID for 1 cycle corresponding to the wrreq valid when a CfgWr Request TLP is received from the PCI Express link.
cfg_wrreq_out_value[3:0] O

Configuration Write Request Output Value:

Shows a 1-cycle pulse of the value corresponding to the wrreq valid when a CfgWr Request TLP is received from the PCI Express link.

When FLR-Vld is asserted:

  • [0]: flr value

When MSI-Vld is asserted:

  • [3:1]: msi_mmenable[2:0] value
  • [0]: msi_enable value

When BME-Vld is asserted:

  • [3]: interrupt_disable write byte enable
  • [2]: interrupt_disable value
  • [1]: bus_master_enable write byte enable
  • [0]: bus_master_enable value

When VFE-Vld is asserted:

  • [0]: vf_enable value

When MSIX-Vld is asserted:

  • [1]: msix_mask value
  • [0]: msix_enable value
cfg_perfunc_out[23:0] O

Per-Function Output:

Status.
  • [0] Bus Master Enable
  • [1] MSIX Enable
  • [2] MSIX Mask
  • [3] Transactions Pending
  • [4] FLR In Progress
  • [5] ATS Control
  • [8:6] For PF: Power State[2:0]
  • [9] For PF: Memory Space Enable
  • [10] For PF: 10-Bit Tag Requester Enable
  • [11] For PF: MSI Enable
  • [14:12] For PF: MSI mmenable[2:0]
  • [15] For PF: IO Space Enable
  • [16] For PF: INTx Disable
  • [17] For PF: RCB Status
  • [18] For PF: Atomic Requester Enable
  • [19] For PF: PASID Enable
  • [20] For PF: PASID Exec Permission Enable
  • [21] For PF: PASID Privil Mode Enable
  • [23:22] For PF: PRI Control
cfg_perfunc_vld O

Per-Function Output Valid:

When asserted, indicates the Per-Function Input Request has been received and the cfg_perfunc_out contains valid output data.
cfg_perfunc_func_num[15:0] I

Per-Function Function ID Input Request:

Valid entries 16'h0000-16'h100F for Function IDs from 0 to 15 (PFs) and 16 to 4111 (VFs). Values 16'h1010-16'hFFFF are reserved.
cfg_perfunc_req I

Per-Function Input Request:

The user application asserts this input to request status of the cfg_perfunc_func_num Function ID. This input must be held asserted until cfg_perfunc_vld is asserted indicating the request has been received.