Simulating the Example Design - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The example design provides a quick way to simulate and observe the behavior of the core for PCI Express® Endpoint and Root port Example design projects generated using the Vivado Design Suite.

The currently supported simulators are:

  • Vivado simulator (default)
  • Questa Advanced Simulator
  • Cadence Incisive Enterprise Simulator (IES)
  • Cadence Xcelium Logic Simulator
  • Synopsys Verilog Compiler Simulator (VCS)

You can generate an example design project and run simulation on the example project. The simulator uses the example design test bench and test cases provided along with the example design for both the design configurations.

A simulation, using the default Vivado simulator, is run as follows:

  1. In the Sources Window, right-click the example project file (.xci), and select Open IP Example Design.

    The example project is created.

  2. In the Flow Navigator (left-hand pane), under Simulation, right-click Run Simulation and select Run Behavioral Simulation.
    Important: The post-synthesis and post-implementation simulation options are not supported for the PCI Express block.

    After the Run Behavioral Simulation Option is running, you can observe the compilation and elaboration phase through the activity in the Tcl Console, and in the Simulation tab of the Log Window.

  3. In Tcl Console, type the run all command and press Enter. This runs the complete simulation as per the test case provided in example design test bench.

    After the simulation is complete, the result can be viewed in the Tcl Console.