Completer Request Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. Completer Request Interface Port Descriptions (512-bit Interface)
Name I/O Width Description
m_axis_cq_tdata O 512 Transmit data from the PCIe completer request interface to the user application.
m_axis_cq_tuser O 231 This is a set of signals containing sideband information for the TLP being transferred. These signals are valid when m_axis_cq_tvalid is High. The individual signals in this set are described in the following table.
m_axis_cq_tlast O 1 The core asserts this signal in the last beat of a packet to indicate the end of the packet. When a TLP is transferred in a single beat, the core sets this bit in the first beat of the transfer. This output is used only when the straddle option is disabled. When the straddle option is enabled, the core sets this output permanently to 0.
m_axis_cq_tkeep O 16 The assertion of bit i of this bus during a transfer indicates to the user logic that Dword i of the m_axis_cq_tdata bus contains valid data. The core sets this bit to 1 contiguously for all Dwords starting from the first Dword of the descriptor to the last Dword of the payload. Thus, m_axis_cq_tdata is set to all 1s in all beats of a packet, except in the final beat when the total size of the packet is not a multiple of the width of the data bus (both in Dwords). This is true for both Dword-aligned and 128b address-aligned modes of payload transfer.

The tkeep bits are valid only when straddle is not enabled on the CQ interface. When straddle is enabled, the tkeep bits are permanently set to all 1s in all beats. The user logic must use the is_sop/is_eop signals in the m_axis_cq_tuser bus in that case to determine the start and end of TLPs transferred over the interface.

m_axis_cq_tvalid O 1 The core asserts this output whenever it is driving valid data on the m_axis_cq_tdata bus. The core keeps the valid signal asserted during the transfer of a packet. The user application can pace the data transfer using the m_axis_cq_tready signal.
m_axis_cq_tready I 1 Activation of this signal by the user logic indicates to the PCIe core that the user logic is ready to accept data. Data is transferred across the interface when both m_axis_cq_tvalid and m_axis_cq_tready are asserted in the same cycle.

If the user logic deasserts the ready signal when m_axis_cq_tvalid is High, the core maintains the data on the bus and keeps the valid signal asserted until the user logic has asserted the ready signal.

pcie_cq_np_req I 2 This input is used by the user application to request the delivery of a Non-Posted request. The core implements a credit-based flow control mechanism to control the delivery of Non-Posted requests across the interface, without blocking Posted TLPs.

This input to the core controls an internal credit count. The credit count is updated in each clock cycle based on the setting of pcie_cq_np_req[1:0] as follows:

  • 00: No change
  • 01: Increment by 1
  • 10 or 11: Increment by 2

The credit count is decremented on the delivery of each Non-Posted request across the interface. The core temporarily stops delivering Non-Posted requests to the user logic when the credit count is zero. It continues to deliver any Posted TLPs received from the link even when the delivery of Non-Posted requests has been paused.

The user application can either set pcie_cq_np_req[1:0] in each cycle based on the status of its Non-Posted request receive buffer, or can set it to 11 permanently if it does not need to exercise selective backpressure on Non-Posted requests.

The setting of pcie_cq_np_req[1:0] does not need to be aligned with the packet transfers on the completer request interface.

pcie_cq_np_req_count O 6 This output provides the current value of the credit count maintained by the core for delivery of Non-Posted requests to the user logic. The core delivers a Non-Posted request across the completer request interface only when this credit count is non-zero. This counter saturates at a maximum limit of 32.

Because of internal pipeline delays, there can be several cycles of delay between the user application providing credit on the pcie_cq_np_req[1:0] inputs and the PCIe core updating the pcie_cq_np_req_count output in response.

This count resets on user_reset and de-assertion of user_lnk_up.

When PASID_CAP_ON is enabled, the m_axis_cq_tuser[228:183] pins are specific to passing PASID field information. In all other cases those fields are reserved. The following table provides more information.
Table 2. Sideband Signals in m_axis_cq_tuser (512-bit Interface)
Bit Index Name Width Description
7:0 first_be[7:0] 8 Byte enables for the first Dword of the payload. first_be[3:0] reflects the setting of the First Byte Enable bits in the Transaction-Layer header of the first TLP in this beat; and first_be[7:4] reflects the setting of the First Byte Enable bits in the Transaction-Layer header of the second TLP in this beat. For Memory Reads and I/O Reads, the 4 bits indicate the valid bytes to be read in the first Dword. For Memory Writes and I/O Writes, these bits indicate the valid bytes in the first Dword of the payload. For Atomic Operations and Messages with a payload, these bits are set to all 1s.

Bits [7:4] of first_be are valid only when straddle is enabled on the CQ interface. When straddle is disabled, these bits are permanently set to 0s.

This field is valid in the first beat of a packet. first_be[3:0] is valid when m_axis_cq_tvalid and is_sop[0] are both asserted High. first_be[7:4] is valid when m_axis_cq_tvalid and is_sop[1] are both asserted High.

15:8 last_be[7:0] 8 Byte enables for the last Dword of the payload. last_be[3:0] reflects the setting of the Last Byte Enable bits in the Transaction-Layer header of the first TLP in this beat; and last_be[7:4] reflects the setting of the Last Byte Enable bits in the Transaction-Layer header of the second TLP in this beat. For Memory Reads, the 4 bits indicate the valid bytes to be read in the last Dword of the block of data. For Memory Writes, these bits indicate the valid bytes in the ending Dword of the payload. For Memory Reads and Writes of one DW transfers and zero length transfers, these bits should be 0s. For Atomic Operations and Messages with a payload, these bits are set to all 1s.

Bits [7:4] of last_be are valid only when straddle is enabled on the CQ interface. When straddle is disabled, these bits are permanently set to 0s.

This field is valid in the first beat of a packet. last_be[3:0] is valid when m_axis_cq_tvalid and is_eop[0] are both asserted High. last_be[7:4] is valid when m_axis_cq_tvalid and is_eop[1] are both asserted High.

79:16 byte_en[63:0] 64 The user logic can optionally use these byte enable bits to determine the valid bytes in the payload of a packet being transferred The assertion of bit i of this bus during a transfer indicates to the user logic that byte i of the m_axis_cq_tdata bus contains a valid payload byte. This bit is not asserted for descriptor bytes.

Although the byte enables can be generated by user logic from information in the request descriptor (address and length) and the settings of the first_be and last_be signals, the user logic has the option of using these signals directly instead of generating them from other interface signals.

When the payload size is more than 2 Dwords (8 bytes), the first bits on this bus for the payload are always contiguous. When the payload size is 2 Dwords or less, the first bits might be non-contiguous.

For the special case of a zero-length memory write transaction defined by the PCI ExpressSpecifications, the byte_en bits are all 0 when the associated 1 Dword payload is being transferred.

81:80 is_sop[1:0] 2 Signals the start of a new TLP in this beat. These outputs are set in the first beat of a TLP. When straddle is disabled, only is_sop[0] is valid and is_sop[1] is permanently set to 0. When straddle is enabled, the settings are as follows:
  • 00: No new TLP starting in this beat.
  • 01: A single new TLP starts in this beat. Its start position is indicated by is_sop0_ptr[1:0].
  • 11: Two new TLPs are starting in this beat. is_sop0_ptr[1:0] provides the start position of the first TLP and is_sop1_ptr[1:0] provides the start position of the second TLP.
  • 10: Reserved.

Use of this signal is optional for the user logic when the straddle option is disabled, because a new TLP always starts in the beat following tlast assertion.

83:82 is_sop0_ptr[1:0] 2 Indicates the position of the first byte of the first TLP starting in this beat:
  • 00: Byte lane 0
  • 10: Byte lane 32
  • 01, 11: Reserved

This field is valid only when the straddle option is enabled on the CQ interface. Otherwise, it is set to 0 permanently, as a TLP can only start in bye lane 0.

85:84 is_sop1_ptr[1:0] 2 Indicates the position of the first byte of the second TLP starting in this beat:
  • 10: Byte lane 32
  • 00, 01, 11: Reserved.

This output is used only when the straddle option is enabled on the CQ interface. The core straddles two TLPs in the same beat. The output is permanently set to 0 when straddle is disabled.

87:86 is_eop[1:0] 2 Indicates that a TLP is ending in this beat. These outputs are set in the final beat of a TLP. When straddle is disabled, only is_eop[0] is valid and is_eop[1] is permanently set to 0. When straddle is enabled, the settings are as follows:
  • 00: No TLPs ending in this beat.
  • 01: A single TLP is ending in this beat. is_eop0_ptr[3:0] provides the offset of the last Dword of this TLP.
  • 11: Two TLPs are ending in this beat. is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP and is_eop1_ptr[3:0]provides the offset of the last Dword of the second TLP.
  • 10: Reserved.

The use of this signal is optional for the user logic when the straddle option is not enabled, because tlast Is asserted in the final beat of a TLP.

91:88 is_eop0_ptr[3:0] 4 Offset of the last Dword of the first TLP ending in this beat. This output is valid when is_eop[0] is asserted.
95:92 is_eop1_ptr[3:0] 4 Offset of the last Dword of the second TLP ending in this beat. This output is valid when is_eop[1] is asserted.

The output is permanently set to 0 when straddle is disabled.

96 discontinue 1 This signal is asserted by the core in the last beat of a TLP, if it has detected an uncorrectable error while reading the TLP payload from its internal FIFO memory. The user application must discard the entire TLP when such an error is signaled by the core.

This signal is never asserted when the TLP has no payload. It is asserted only in the last beat of the payload transfer, that is when is_eop[0] is High.

When the straddle option is enabled, the core does not start a second TLP if it has asserted discontinue in a beat.

When the core is configured as an Endpoint, the error is also reported by the core to the Root Complex it is attached to, using Advanced Error Reporting (AER).

182:119 parity 64 Odd parity for the 512-bit transmit data. Bit i provides the odd parity computed for byte i of m_axis_cq_tdata.
183 PASID TLP Valid 0 1 Indicates PASID TLP 0 is valid.
184 PASID TLP Valid 1 1 Indicates PASID TLP 1 is valid.
204:185 PASID 0 20 Indicates PASID TLP Prefix for packet0 to the user design.
224:205 PASID 1 20 Indicates PASID TLP Prefix for packet1 to the user design.
225 Execute Requested 0 1 Indicates Execute Requested for packet0
226 Execute Requested 1 1 Indicates Execute Requested for packet1
227 Privileged Mode Requested 0 1 Indicates Privileged Mode Requested for packet0 to the user design.
228 Privileged Mode Requested 1 1 Indicates Privileged Mode Requested for packet 1 to the user design.
230:229 poisoned_tlp[1:0] 2 Indicates poisoned bit set on received TLPs.
  • 00 - No poisoned TLP received
  • 01 - One poisoned TLP received at location determined by is_sop0_ptr[1:0]
  • 11 - Two poisoned TLPs received at locations determined by is_sop0_ptr[1:0] and is_sop1_ptr[1:0]