Ports - 1.1 English - PG343

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID: PG343
Release Date: 2025-05-29
Version: 1.1 English

Introduction
PL PCIE4 Features
PL PCIE5 Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Applications
Unsupported Features
Limitations
Licensing and Ordering
Product Specification
Standards for the Integrated Block IP
Performance and Resource Use
Minimum Device Requirements
Port Descriptions
AXI4-Stream Core Interfaces
64/128/256-bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
512-bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
Other Core Interfaces
Power Management Interface
Configuration Management Interface
Configuration Status Interface
Configuration Received Message Interface
Configuration Transmit Message Interface
Configuration Flow Control Interface
Configuration Interface
Configuration Control Interface
Configuration Interrupt Controller Interface
Legacy Interrupt Interface
MSI Interrupt Interface
MSI-X Interrupt External Interface
MSI-X Interrupt Internal Interface
Configuration Extend Interface
Configuration VC1 Status Interface
Configuration PASID Interface
APB3 Interface
Clock and Reset Interface
PCIe PHY IP Interface
Clock and Reset Signals
TX Data Signals
RX Data Signals
Command Signals
Status Signals
TX Driver Signals for Gen1 and Gen2
Configuration Space
Designing with the Core
Clocking
Resets
AXI4-Stream Interface Description
Feature Overview
Supported Clock Frequencies and Interface Widths
Data Alignment Options
Straddle Option on CQ, CC, and RQ Interfaces
Straddle Option on RC Interface
Receive Transaction Ordering
Transmit Transaction Ordering
64/128/256-bit Completer Interface
Completer Request Interface Operation
Completer Request Descriptor Formats
Completer Memory Write Operation
Completer Memory Read Operation
I/O Write Operation
I/O Read Operation
Atomic Operations on the Completer Request Interface
Message Requests on the Completer Request Interface
Aborting a Transfer
Selective Flow Control for Non-Posted Requests
Completer Completion Interface Operation
Completer Completion Descriptor Format
Completions with Successful Completion Status
Aborting a Completion Transfer
Completions with Error Status (UR and CA)
64/128/256-bit Requester Interface
Requester Request Interface Operation
Requester Request Descriptor Formats
Requester Memory Write Operation
Non-Posted Transactions with No Payload
Non-Posted Transactions with a Payload
Message Requests on the Requester Interface
Aborting a Transfer
Tag Management for Non-Posted Transactions
Avoiding Head-of-Line Blocking for Posted Requests
Maintaining Transaction Order
Requester Completion Interface Operation
Requester Completion Descriptor Format
Transfer of Completions with No Data
Transfer of Completions with Data
Straddle Option for 256-Bit Interface
Aborting a Completion Transfer
Handling of Completion Errors
512-bit Completer Interface
Completer Request Interface Operation (512-bit)
Completer Request Descriptor Formats
Completer Memory Write Operation
Completer Memory Read Operation
I/O Write Operation
I/O Read Operation
Atomic Operations on the Completer Request Interface
Message Requests on the Completer Request Interface
Aborting a Transfer
Selective Flow Control for Non-Posted Requests
Straddle Option on CQ Interface
Completer Completion Interface Operation (512-bit)
Completer Completion Descriptor Format
Completions with Successful Completion (SC) Status
Aborting a Completion Transfer
Completions with Error Status (UR and CA)
Straddle Option on CC Interface
512-bit Requester Interface
Requester Request Interface Operation (512-bit)
Requester Request Descriptor Formats
Requester Memory Write Operation
Non-Posted Transactions with No Payload
Non-Posted Transactions with a Payload
Message Requests on the Requester Interface
Aborting a Transfer
Straddle Option on RQ Interface
Tag Management for Non-Posted Transactions
Avoiding Head-of-Line Blocking for Posted Requests
Maintaining Transaction Order
Requester Completion Interface Operation (512-bit)
Requester Completion Descriptor Format
Transfer of Completions with No Data
Transfer of Completions with Data
Straddle Option for RC Interface
Aborting a Completion Transfer
Handling of Completion Errors
Power Management
Active State Power Management
Programmed Power Management
PPM L0 State
PPM L1 State
PPM L3 State
Generating Interrupt Requests
Legacy Interrupt Mode
MSI Mode
MSI-X Mode
MSI-X Mode with Built-in MSI-X Vector Tables
Receive Message Interface
Configuration Management Interface
Enabling Loopback Master on Root Port
Link Training: 2-Lane, 4-Lane, 8-Lane, and 16-Lane Components
Link Partner Supports Fewer Lanes
Lane Becomes Faulty
Lane Reversal
Design Flow Steps
Customizing and Generating the Core
Basic Mode Parameters
Basic Tab
Capabilities Tab
PF IDs Tab
PF BARs Tab
Legacy/MSI Cap Tab
Advanced Mode Parameters
Basic Tab
Capabilities Tab
SRIOV Config Tab
SRIOV VF BARs Tab
MSI-X Capabilities Tab
Advanced Options Tab
Output Generation
Connecting the Core
Run Block Automation in IP Integrator
Constraining the Core
Required Constraints
Clock Frequencies, Management, and Placement
Banking
Transceiver Placement
I/O Standard and Placement
Relocating the Integrated Block Core
Simulation
Synthesis and Implementation
Example Design
Overview of the Example Design
Integrated Block Endpoint Configuration Overview
Simulation Design Overview
Implementation Design Overview
Example Design Elements
Programmed Input/Output: Endpoint Example Design
System Overview
PIO Hardware
Base Address Register Support
Changing IP Catalog Tool Default BAR Settings
TLP Data Flow
Memory and I/O Write TLP Processing
Memory and I/O Read TLP Processing
PIO File Structure
PIO Operation
PIO Read Transaction
PIO Write Transaction
Configurator: Rootport Example Design
Configurator File Structure
Bus Master DMA: Endpoint Example Design
Target Logic
Control and Status Registers
Initiator Logic
Generating the Core
Opening the Example Design
Simulating the Example Design
Endpoint Configuration
Synthesizing and Implementing the Example Design
Test Bench
Root Port Model Test Bench for Endpoint
Architecture
Scaled Simulation Timeouts
Test Selection
Available Tests
Verilog Test Selection
Waveform Dumping
Verilog Flow
Output Logging
Parallel Test Programs
Completer Model
Test Description
Test Program: pio_writeReadBack_test0
Expanding the Root Port Model
Root Port Model TPI Task List
Test Setup Tasks
TLP Tasks
BAR Initialization Tasks
Example PIO Design Tasks
Expectation Tasks
Endpoint Model Test Bench for Root Port
Architecture
Simulating the Design
Scaled Simulation Timeouts
Waveform Dumping
Output Logging
Upgrading
Migrating from UltraScale+™ PCIe core to Versal PL PCIE4
Ports
New Ports
Port Updates
Ports Not Available
Generating GT and PHY IP
Clocking
Reset
Features
New Features
Features Not Available, or Limited Usage Features
Migrating from UltraScale+™ PCIe core to Versal PL PCIE5
Ports
New Ports
Port Updates
Ports Not Available
Generating GT and PHY IP
Clocking
Reset
Features
New Features
Features Not Available, or Limited Usage Features
GT Selection and Pin Planning
PL PCIe GT Selection
CPM4 Additional Considerations
GT Locations
Assigning GT Locations
GT Quad Locations
GT Selection and Pin Planning for Versal Premium
GT Locations
Assigning GT Locations
GT Quad Locations
PCIe Link Debug Enablement
Enabling PCIe Link Debug
Connecting to PCIe Link Debug in Vivado
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Debug Guide
Answer Records
Master Answer Record for the Core
Technical Support
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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