Straddle Option for 256-Bit Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

When the interface width is configured as 256 bits, the integrated block can start a new Completion transfer on the RC interface in the same beat when the previous Completion has ended on or before Dword position 3 on the data bus. The straddle option can be used only with the Dword-aligned mode.

When the straddle option is enabled, Completion TLPs are transferred on the RC interface as a continuous stream, with no packet boundaries (from an AXI4-Stream perspective). Thus, the m_axis_rc_tkeep and m_axis_rc_tlast signals are not useful in determining the boundaries of Completion TLPs delivered on the interface (the integrated block sets m_axis_rc_tkeep to all 1s and m_axis_rc_tlast to 0 permanently when the straddle option is in use). Instead, delineation of TLPs is performed using the following signals provided within the m_axis_rc_tuser bus:

  • is_sof_0: The integrated block drives this output active-High in a beat when there is at least one Completion TLP starting in the beat. The position of the first byte of this Completion TLP is determined as follows:
    • If the previous Completion TLP ended before this beat, the first byte of this Completion TLP is in byte lane 0.
    • If a previous TLP is continuing in this beat, the first byte of this Completion TLP is in byte lane 16. This is possible only when the previous TLP ends in the current beat, that is when is_eof_0[0] is also set.
  • is_sof_1: The integrated block asserts this output in a beat when there are two Completion TLPs starting in the beat. The first TLP always starts at byte position 0 and the second TLP at byte position 16. The integrated block starts a second TLP at byte position 16 only if the previous TLP ended before byte position 16 in the same beat, that is only if is_eof_0[0] is also set in the same beat.
  • is_eof_0[3:0]: These outputs are used to indicate the end of a Completion TLP and the position of its last Dword on the data bus. The assertion of the bit is_eof_0[0] indicates that there is at least one Completion TLP ending in this beat. When bit 0 of is_eof_0 is set, bits [3:1] provide the offset of the last Dword of the TLP ending in this beat. The offset for the last byte can be determined from the starting address and length of the TLP, or from the byte enable signals byte_en[31:0]. When there are two Completion TLPs ending in a beat, the setting of is_eof_0[3:1] is the offset of the last Dword of the first Completion TLP (in that case, its range is 0 through 3).
  • is_eof_1[3:0]: The assertion of is_eof_1[0] indicates a second TLP ending in the same beat. When bit 0 of is_eof_1 is set, bits [3:1] provide the offset of the last Dword of the second TLP ending in this beat. Because the second TLP can start only on byte lane 16, it can only end at a byte lane in the range 27–31. Thus the offset is_eof_1[3:1] can only take one of two values: 6 or 7. If is_sof_1[0] is active-High, the signals is_eof_0[0] and is_sof_0 are also active-High in the same beat. If is_sof_1 is active-High, is_sof_0 is active-High. If is_eof_1 is active-High, is_eof_0 is active-High.

The following figure illustrates the transfer of four Completion TLPs on the 256-bit RC interface when the straddle option is enabled. The first Completion TLP (COMPL 1) starts at Dword position 0 of Beat 1 and ends in Dword position 0 of Beat 3. The second TLP (COMPL 2) starts in Dword position 4 of the same beat. This second TLP has only a one-Dword payload, so it also ends in the same beat. The third and fourth Completion TLPs are transferred completely in Beat 4, because Completion 3 has only a one-Dword payload and Completion 4 has no payload.

Figure 1. Transfer of Completion TLPs on the Requester Completion Interface with the Straddle Option Enabled