Opening the Example Design - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
  1. To open IP example design, right-click on the generated IP core, and select Open IP Example Design.
    Note: For core generation, see the Generating the Core section above.


  2. In the open window, click OK. Vivado creates a directory named <core name>_ex in the Example project directory. Adjust the path if needed, and click OK.

The generated example design consists of two block designs:

  • endpoint (design_ep)
  • root port (design_rp)
The block design for a Gen4x4 PCIe endpoint example design is shown below:

  • The pcie_versal_0 block is the PCIe IP Core with the configuration set before opening example design.
  • The pcie_phy and gt_quad_0 blocks are the PHY IP and GT Wizard for the PCIe core. Unlike in AMD UltraScale+™ devices, where the PHY IP and GT Wizard are within PCIe IP, in Versal device, the two blocks are external to PCIe IP core.
  • The refclk_ibuf, bufg_gt_sysclk, and const_1b1 blocks are used for the sys_clk buffer. The refclk_ibuf block is taking input clock pins sys_clk_n and sys_clk_p. The output of the bufg_gt_sysclk is the system reference clock, which is input for PCIe IP. Similar to UltraScale+, sys_rst_n is also an input, and all three inputs are constrained in the top XDC file.
  • The Root Port block design is similar to Endpoint, and has an PCIe core with the required blocks generated. Root Port block design is used in simulation.