Configuration Extend Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The Configuration Extend interface allows the core to transfer configuration information with the user application when externally implemented configuration registers are implemented. The following table defines the ports in the Configuration Extend interface of the core.

Table 1. Configuration Extend Interface Port Descriptions
Port I/O Width Description
cfg_ext_read_received O 1 Configuration Extend Read Received.

The Block asserts this output when it has received a configuration read request from the link.

Set when PCI Express Extended Configuration Space Enable is selected in User Defined Configuration Capabilities in core configuration in the Vivado IDE.

All received configuration reads with cfg_ext_register_number in the following ranges is considered to be the PCIe Extended Configuration Space.

  • AMD Versalâ„¢ PCIe core: 0xE80-0xFFF

All the received configuration reads regardless of their address are indicated by 1 cycle assertion of cfg_ext_read_received and valid data is driven on cfg_ext_register_number and cfg_ext_function_number.

Only received configuration reads within the aforementioned ranges need to be responded by User Application outside of the IP.

cfg_ext_write_received O 1 Configuration Extend Write Received.

The Block asserts this output when it has received a configuration write request from the link.

Set when PCI Express Extended Configuration Space Enable is selected in User Defined Configuration Capabilities in the core configuration in the Vivado IDE.

Data corresponding to all received configuration writes with cfg_ext_register_number in the range 0xb0-0xbf is presented on cfg_ext_register_number, cfg_ext_function_number, cfg_ext_write_data, and cfg_ext_write_byte_enable.

All received configuration writes with cfg_ext_register_number in the following ranges are presented on cfg_ext_register_number, cfg_ext_function_number, cfg_ext_wrte_data, and cfg_ext_write_byte_enable.

  • Versal PCIe core: 0xE80-0xFFF
cfg_ext_register_number O 10 Configuration Extend Register Number

The 10-bit DWORD address of the configuration register being read or written. For example, to access the 0x480 address, 0x480/4 = 0x120 should be placed on cfg_ext_register_number because this is DWORD address. The data is valid when cfg_ext_read_received or cfg_ext_write_received is High.

cfg_ext_function_number O 8 Configuration Extend Function Number

The function number corresponding to the configuration read or write request. The data is valid when cfg_ext_read_received or cfg_ext_write_received is High.

cfg_ext_write_data O 32 Configuration Extend Write Data

Data being written into a configuration register. This output is valid when cfg_ext_write_received is High.

cfg_ext_write_byte_enable O 4 Configuration Extend Write Byte Enable

Byte enables for a configuration write transaction.

cfg_ext_read_data I 32 Configuration Extend Read Data

You can provide data from an externally implemented configuration register to the core through this bus. The core samples this data on the next positive edge of the clock after it sets cfg_ext_read_received High, if you have set cfg_ext_read_data_valid.

cfg_ext_read_data_valid I 1 Configuration Extend Read Data Valid

The user application asserts this input to the core to supply data from an externally implemented configuration register. The core samples this input data on the next positive edge of the clock after it sets cfg_ext_read_received High. The core expects the assertions of this signal within 262144 ('h4_0000) clock cycles of user clock after receiving the read request on cfg_ext_read_received signal. If no response is received by this time, the core sends auto-response with 'h0 payload, and the user application must discard the response and terminate that particular request immediately.