Non-Posted Transactions with No Payload - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

Non-Posted transactions with no payload (memory read requests, I/O read requests, Configuration read requests) are transferred across the requester request interface in the same manner as a memory write request, except that the AXI4-Stream packet contains only the 16-byte descriptor. The following figure illustrates the transfer of a memory read request across the requester request interface. The signal s_axis_rq_tvalid must remain asserted over the duration of the packet. The core are pull down s_axis_rq_tready to prolong the beat. The signal s_axis_rq_tlast must be set in the last beat of the packet, and the bits in s_axis_rq_tkeep[15:0] must be set in all Dword positions where a descriptor is present.

The user application must indicate the valid bytes in the first and last Dwords of the data block using the fields first_be[7:0] and last_be[7:0], respectively, in the s_axis_rq_tuser bus. For the special case of a zero-length memory read, the length of the request must be set to one Dword, with both first_be[7:0] and last_be[7:0] set to all 0s. The user application must also communicate the offset of the first Dword of the payload of the resulting Completion, when delivered over the requester completion interface, in the addr_offset[3:0] field of the s_axis_rq_tuser bus. In Straddled case, addr_offset[3:2], first_be[7:4], and last_be[7:4] are used to indicate second TLP information while addr_offset[1:0], first_be[3:0], and last_be[3:0] are used to indicate the first TLP information on that data beat.

Figure 1. Memory Read Transaction on the Requester Request Interface