Requester Request Interface Operation - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

On the RQ interface, the user application delivers each TLP as an AXI4-Stream packet. The packet starts with a 128-bit descriptor, followed by data in the case of TLPs with a payload. The following figure shows the signals associated with the requester request interface.

Figure 1. Requester Request Interface

The RQ interface supports two distinct data alignment modes for transferring payloads. In the Dword-aligned mode, the user logic must provide the first Dword of the payload immediately after the last Dword of the descriptor. It must also set the bits in first_be[3:0] to indicate the valid bytes in the first Dword and the bits in last_be[3:0] (both part of the bus s_axis_rq_tuser) to indicate the valid bytes in the last Dword of the payload. In the address-aligned mode, the user application must start the payload transfer in the beat following the last Dword of the descriptor, and its first Dword can be in any of the possible Dword positions on the datapath. The user application communicates the offset of the first Dword on the datapath using the addr_offset[2:0] signals in s_axis_rq_tuser. As in the case of the Dword-aligned mode, the user application must also set the bits in first_be[3:0] to indicate the valid bytes in the first Dword and the bits in last_be[3:0] to indicate the valid bytes in the last Dword of the payload.