Example PIO Design Tasks - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. Example PIO Design Tasks
Name Input(s) Description
TSK_TX_READBACK_CONFIG None

Performs a sequence of PCI Type 0 Configuration Reads to the Endpoint device Base Address Registers, PCI Command register, and PCIe Device Control register using the PCI Express logic.

This task should only be called after TSK_SYSTEM_INITIALIZATION.

TSK_MEM_TEST_DATA_BUS bar_index 2:0

Tests whether the PIO design Versal device block RAM data bus interface is correctly connected by performing a 32-bit walking ones data test to the I/O or memory address pointed to by the input bar_index.

For an exhaustive test, this task should be called four times, once for each block RAM used in the PIO design.

TSK_MEM_TEST_ADDR_BUS

bar_index

nBytes

2:0

31:0

Tests whether the PIO design Versal device block RAM address bus interface is accurately connected by performing a walking ones address test starting at the I/O or memory address pointed to by the input bar_index.

For an exhaustive test, this task should be called four times, once for each block RAM used in the PIO design. Additionally, the nBytes input should specify the entire size of the individual block RAM.

TSK_MEM_TEST_DEVICE

bar_index

nBytes

2:0

31:0

Tests the integrity of each bit of the PIO design Versal device block RAM by performing an increment/decrement test on all bits starting at the block RAM pointed to by the input bar_index with the range specified by input nBytes.

For an exhaustive test, this task should be called four times, once for each block RAM used in the PIO design. Additionally, the nBytes input should specify the entire size of the individual block RAM.

TSK_RESET Reset 0 Initiates sys_rst_n signal in board.v file. Forces the sys_rst_n signal to assert the reset. Use TSK_RESET (1'b1) to assert the reset and TSK_RESET (1'b0) to release the reset signal.
TSK_MALFORMED malformed_bits 7:0

Control bits for creating malformed TLPs:

0001: Generate Malformed TLP for I/O Requests and Configuration Requests called immediately after this task

0010: Generate Malformed Completion TLPs for Memory Read requests received at the Root Port