Configuration Received Message Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
Document ID
PG343
Release Date
2024-11-22
Version
1.0 English
The Configuration Received Message interface indicates to the logic that a decodable message from the link, the parameters associated with the data, and the type of message received. The following table defines the ports in the Configuration Received Message interface of the core.
Table 1. Configuration Received Message Interface
Port I/O Width Description
cfg_msg_received O 1 Configuration Received a Decodable Message.

The core asserts this output for one or more consecutive clock cycles when it has received a decodable message from the link. The duration of its assertion is determined by the type of message. The core transfers any parameters associated with the message on the cfg_msg_data[7:0]output in one or more cycles when cfg_msg_received is High. Table 3 lists the number of cycles of cfg_msg_received assertion, and the parameters transferred on cfg_msg_data[7:0] in each cycle, for each type of message.

The core inserts at least a one-cycle gap between two consecutive messages delivered on this interface when the cfg_msg_received interface is enabled.

The Configuration Received Message interface must be enabled during core configuration in the Vivado IDE.
cfg_msg_received_data O 8 This bus is used to transfer any parameters associated with the Received Message. The information it carries in each cycle for various message types is listed in Table 3.
cfg_msg_received_type O 5 Received message type.

When cfg_msg_received is High, these five bits indicate the type of message being signaled by the core. The various message types are listed in Table 3.
Table 2. Message Type Encoding on Receive Message Interface
cfg_msg_received_type[4:0] Message Type
0 ERR_COR
1 ERR_NONFATAL
2 ERR_FATAL
3 Assert_INTA
4 Deassert_ INTA
5 Assert_INTB
6 Deassert_ INTB
7 Assert_INTC
8 Deassert_ INTC
9 Assert_INTD
10 Deassert_ INTD
11 PM_PME
12 PME_TO_Ack
13 PME_Turn_Off
14 PM_Active_State_Nak
15 Set_Slot_Power_Limit
16 Latency Tolerance Reporting (LTR)
17 Reserved
18 Unlock
19 Vendor_Defined Type 0
20 Vendor_Defined Type 1
25 – 31 Reserved
Table 3. Message Parameters on Receive Message Interface
Message Type Number of cycles of cfg_msg_received assertion Parameter transferred on cfg_msg_received_data[7:0]
ERR_COR, ERR_NONFATAL, ERR_FATAL 2 Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number
Assert_INTx, Deassert_INTx 2 Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number
PM_PME, PME_TO_Ack, PME_Turn_off, PM_Active_State_Nak 2 Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number
Set_Slot_Power_Limit 6 Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number

Cycle 3: bits [7:0] of payload

Cycle 4: bits [15:8] of payload

Cycle 5: bits [23:16] of payload

Cycle 6: bits [31:24] of payload
Latency Tolerance Reporting (LTR) 6 Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number

Cycle 3: bits [7:0] of Snoop Latency

Cycle 4: bits [15:8] of Snoop Latency

Cycle 5: bits [7:0] of No-Snoop Latency

Cycle 6: bits [15:8] of No-Snoop Latency
Unlock 2 Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number
Vendor_Defined Type 0 4 cycles when no data present, 8 cycles when data present. Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number

Cycle 3: Vendor ID[7:0]

Cycle 4: Vendor ID[15:8]

Cycle 5: bits [7:0] of payload

Cycle 6: bits [15:8] of payload

Cycle 7: bits [23:16] of payload

Cycle 8: bits [31:24] of payload
Vendor_Defined Type 1 4 cycles when no data present, 8 cycles when data present. Cycle 1: Requester ID, Bus Number

Cycle 2: Requester ID, Device/Function Number

Cycle 3: Vendor ID[7:0]

Cycle 4: Vendor ID[15:8]

Cycle 5: bits [7:0] of payload

Cycle 6: bits [15:8] of payload

Cycle 7: bits [23:16] of payload

Cycle 8: bits [31:24] of payload