Legacy/MSI Cap Tab - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-11-22
Version
1.0 English

On this page, you set the Legacy Interrupt Settings and MSI Capabilities for all applicable physical and virtual functions. This page is not visible when the SRIOV Capability parameter is selected on the Capabilities page.

Figure 1. Legacy/MSI Cap Tab
Legacy Interrupt Settings
PF0/PF1/PF2/PF3 Interrupt PIN
Indicates the mapping for Legacy Interrupt messages. A setting of None indicates that no Legacy Interrupts are used.
Note: When PASID is enabled, legacy interrupts cannot be used and are disabled.
MSI Capabilities
PF0/PF1/PF2/PF3 Enable MSI Capability
Indicates that the MSI Capability structure exists.
Note: Although it is possible to not enable MSI or MSI-X, the result would be a non-compliant core. The PCI Express Base Specification requires that MSI, MSI-X, or both be enabled. No MSI capabilities are supported when MSI-X Internal is enabled in the MSI-X Capabilities Tab (Advanced mode), because MSI-X Internal uses some of the MSI interface signals.
PF0/PF1/PF2/PF3 Multiple Message Capable
Selects the number of MSI vectors to request from the Root Complex.