Programmed Power Management - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
To achieve considerable power savings on the PCI Express® hierarchy tree, the core supports these link states of Programmed Power Management (PPM):
  • L0: Active State (data exchange state)
  • L1: Higher Latency, lower power standby state
  • L3: Link Off State

The Programmed Power Management Protocol is initiated by the Downstream Component/Upstream Port.