MSI-X Mode with Built-in MSI-X Vector Tables - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The core optionally supports built-in MSI-X vector tables including the Pending Bit Array.

  • As shown in the following figure, the user application first asserts cfg_interrupt_msix_int with the vector number set in cfg_interrupt_msi_int.
  • The core asserts cfg_interrupt_msi_sent to signal that the interrupt is accepted. If cfg_interrupt_msix_vec_pending_status is clear, the core sends a MSI-X Memory Write TLP. Otherwise, the core waits to send a MSI-X Memory Write TLP until the function mask is cleared.
Figure 1. MSI-X Signaling with Built-In MSI-X Vector Tables
  • Instead of generating an interrupt, the user application can query or clear the Pending Bit Array by additionally setting cfg_interrupt_msix_vec_pending to 2'b01 or 2'b10 respectively, as shown in the following figure.
  • In the query and clear cases, cfg_interrupt_msix_vec_pending_status reflects the pending status before the query or clear.
  • cfg_interrupt_msi_int[31:0] is a shared signal between MSI [31:0] and MSI-X [7:0].
Figure 2. MSI-X Pending Bit Array Query and Clear
Note: Applications that need to generate MSI/MSI-X interrupts with traffic class bits not equal to 0 or address translation bits not equal to 0 must use the RQ interface to generate the interrupt (memory write descriptor).