PIO Write Transaction - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

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1.0 English

The figure below depicts a back-to-back Memory Write to the PIO design. The next Write transaction is accepted only after wr_busy_o is deasserted by the memory access unit, indicating that data associated with the first request was successfully written to the memory aperture.

Figure 1. Back-to-Back Write Transactions