PCIe PHY IP Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The signals described in this section are based on a single-lane application. Signals can be per lane or per design; if not indicated in the description, the default is per design. Per design indicates that one signal controls all lanes (0 to N-1 lane). A per-lane signal on the PCIe PHY IP is in the form of {LaneN-1[Width-1:0], …Lane1 [Width-1:0], Lane0[Width-1:0]}.