Unsupported Features - 1.0 English

The PCI Express Base Specification 4.0 has many optional features. The following features are not supported in the core:

• ASPM L1/L0s is not supported for root port mode
• Resizable BAR extended capability
• ID-based TLP ordering
• TPH capability
• Fast PCI Express endpoint enumeration using tandem configuration
• MCAP Interface for Partial Configuration and Reconfiguration
• WAKE and CLKREQ are optional signals not supported in the IP
• PCIe beacon transmit and receive is not supported
• This IP architecture assumes exclusive use of one or more complete GT quads, regardless of the designed link width. While it might be possible to share unused lanes in the GT quad with other instances of this IP, non-PCIe IPs, or custom GT-based interfaces for x2 and x1 link widths. AMD does not support evaluations or implementations of such sharing arrangements. The feasibility of sharing depends on the specific GT configuration required for other protocols, links, and lanes intended to share the GT quad. Factors affecting GT configuration include external REFCLKs, fabric design clocks and resets, GT clock management resources, connectivity rules, mode, and electrical settings.