New Features - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

PASID

PASID Extended Capability structure has been added with which the core supports sending and receiving TLPs containing a PASID TLP Prefix.

10 Bit Tag

The PCIe controller supports 10-bit Tag feature, when enabled management of up to 768 tags is possible.

Feature DLLP

Data Link Feature Extended Capability structure has been added for link speed of 16.0 GTps. It contains programmable control/status information about the local and peer support of the Data Link Feature Support.

Lane Margining

Lane Margining at the Receiver Extended Capability structure has been added for link speed of 16.0 GTps and 32.0 GTps.

Physical Layer 16.0 GTps Extended Capability

Physical Layer 16.0 GTps Extended Capability structure has been added for link speed of 16.0 GTps with which Gen4 equalization status can be read.

Physical Layer 32.0 GTps Extended Capability

Physical Layer 32.0 GTps Extended Capability structure has been added for link speed of 32.0 GTps with which Gen5 equalization status can be read.

Retimers Supported

Link extension devices (retimers) is supported to interoperate with CPM4 PCIe block for link speed of 16.0 GTps and 32.0 GTps.

Flow Control Informational Select

More combinations of cfg_fc_sel values are supported relative to UltraScale+. See the port description for more details.

Physical and Virtual Functions

PCIe controller supports up to 8 Physical functions and 4080 Virtual functions as compared to 4 Physical and 252 Virtual functions in UltraScale+.

MSIX – Additional Vectors

When configured as internal, can support up to 2k vectors per physical function as compared to 8 vectors per function for VF in UltraScale+. The total number of vectors increases to 32k vectors accordingly.