Example Design Elements - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The PIO example design elements include:

  • Core wrapper
  • An example Verilog HDL wrapper (instantiates the cores and example design)
  • A customizable demonstration test bench to simulate the example design

The example design has been tested and verified with Vivado Design Suite and these simulators:

  • Vivado simulator
  • Questa Advanced Simulator
  • Synopsys Verilog Compiler Simulator (VCS)

For the supported versions of these tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).