Active State Power Management - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The core advertises an N_FTS value of 255 to ensure proper alignment when exiting L0s. If the N_FTS value is modified, you must ensure enough FTS sequences are received to properly align and avoid transition into the Recovery state.

The Active State Power Management (ASPM) functionality is autonomous and transparent from a user-logic function perspective. The core supports the conditions required for ASPM. The integrated block supports ASPM L0s and ASPM L1. L0s and L1 should not be enabled in parallel.

  • ASPM is not supported in non-synchronous clocking mode.
  • L0s is supported only on designs generated for Gen1and Gen2 and in Endpoint modes only.
  • Enabling ASPM L0s/ASPM L1 can show correctable errors being reported on the link by both link partners (for example, replay timer timeout, replay timer rollover, or receiver error). AMD recommends that the application disables correctable error reporting or ignores correctable errors reported when the ASPM L0s/ASPM L1 transition is initiated.