Straddle Option on CC Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The core has the capability to start the transfer of a new Completion packet on the completer completion interface in the same beat when the previous request has ended on or before Dword position 7 on the data bus. This straddle option is enabled during core customization in the AMD Vivado™ IDE. The straddle option can be used only with the Dword-aligned mode.

When the straddle option is enabled, Completion TLPs are transferred on the AXI4-Stream interface as a continuous stream, with no packet boundaries. Thus, the signals m_axis_cc_tkeep and m_axis_cc_tlast are not useful in determining the boundaries of TLPs delivered on the interface. Instead, delineation of TLPs is performed using the following signals provided within the m_axis_cc_tuser bus.

  • is_sop[0]: This input must be set High in a beat when there is at least one Completion TLP starting in the beat. The position of the first byte of the descriptor of this TLP is determined as follows:
    • If the previous TLP ended before this beat, the first byte of the descriptor is in byte lane 0.
    • If a previous TLP is continuing in this beat, the first byte of this descriptor is in byte lane 32. This is possible only when the previous TLP ends in the current beat, that is when is_eop[0] is also set.
  • is_sop0_ptr[1:0]: When is_sop[0] is set, this field must indicate the offset of the first Completion TLP starting in the current beat. Valid settings are 2'b00 (TLP starting at Dword 0) and 2'b10 (TLP starting at Dword 8).
  • is_sop[1]: This input must be set High in a beat when there are two Completion TLPs starting in the same beat. The first TLP must always start at byte position 0 and the second TLP at byte position 32. The user application are start a second TLP at byte position 32 only if the previous TLP ended before byte position 32 in the same beat, that is only if is_eop[0] is also set in the same beat.
  • is_sop1_ptr[1:0]: When is_sop[1] is set, this field must provide the offset of the second TLP starting in the current beat. Its only valid setting is 2'b10 (TLP starting at Dword 8).
  • is_eop[0]: This input is used to indicate the end of a Completion TLP. Its assertion signals that there is at least one TLP ending in this beat.
  • is_eop0_ptr[3:0]: When is_eop[0] is asserted, is_eop0_ptr[3:0] must provide the offset of the last Dword of the corresponding TLP ending in this beat.
  • is_eop[1]: This input is set High when there are two TLPs ending in the current beat. is_eop[1] can be set only when the signals is_eop[0] and is_sop[0] are also be High in the same beat.
  • is_eop1_ptr[3:0]: When is_eop[1] is asserted, is_eop1_ptr[3:0] must provide the offset of the last Dword of the second TLP ending in this beat. Because the second TLP can start only on byte lane 32, it can only end at a byte lane in the range 43-63. Thus the offset is_eop1_ptr[3:0] can only take a value in the range 10-15.

The following figure illustrates the transfer of four Completion TLPs on the completer completion interface when the straddle option is enabled. For all TLPs, the first Dword of the payload always follows the descriptor without any gaps. The first Completion TLP (COMPL 1) starts at Dword position 0 of Beat 1 and ends in Dword position 5 of Beat 3. The second TLP (COMPL 2) starts in Dword position 8 of the same beat. This second TLP has only a four-Dword payload, so it also ends in the same beat. The third and fourth Completion TLPs are transferred completely in Beat 4, as COMPL 3 has only a one-Dword payload and COMPL 4 has no payload.

Figure 1. Transfer of Completion TLPs on the Completer Completion Interface with the Straddle Option Enabled (512-bit Interface)