Programmed Input/Output: Endpoint Example Design - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

Programmed Input/Output (PIO) transactions are generally used by a PCI Express® system host CPU to access Memory Mapped Input/Output (MMIO) and Configuration Mapped Input/Output (CMIO) locations in the PCI Express logic. Endpoints for PCI Express accept Memory and I/O Write transactions and respond to Memory and I/O Read transactions with Completion with Data transactions.

The PIO example design (PIO design) is included with the core in Endpoint configuration generated by the AMD Vivado™ IP Core catalog, which allows you to bring up your system board with a known established working design to verify the link and functionality of the board.

This section generically represents all solutions using the name Endpoint for PCI Express (or Endpoint for PCIe® ).