Message Requests on the Completer Request Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

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1.0 English

The transfer of a message on the completer request interface is similar to that of a memory write request, except that a payload are not always be present. The transfer starts with the 128-bit descriptor, followed immediately by the payload, if present. The payload always starts in byte lane 16, regardless of the addressing mode in use. The user logic can determine the end of the payload from the states of the signals m_axis_cq_tlast and m_axis_cq_tkeep. The byte_en signals in m_axis_cq_tuser also indicate the valid bytes in the payload. The First Byte Enable and Last Byte Enable bits in m_axis_cq_tuser should not be used.

The attribute ATTR_AXISTEN_IF_ENABLE_RX_MSG_INTFC must be set to 0 to enable the delivery of messages through the completer request interface. When this attribute is set to 0, the attribute ATTR_AXISTEN_IF_ENABLE_MSG_ROUTE can be used to select the specific message types that the user wants delivered over the completer request interface. Setting an attribute bit to 1 enables the delivery of the corresponding type of messages on the interface, and setting it to 0 results in the core filtering the message.

Table 1. AXISTEN_IF_ENABLE_MSG_ROUTE Attribute Bit Descriptions
Bit Index Message Type
3 Assert_INTA and Deassert_INTA
4 Assert_INTB and Deassert_INTB
5 Assert_INTC and Deassert_INTC
6 Assert_INTD and Deassert_INTD
8 PME_TO_Ack
9 PME_Turn_Off
10 PM_Active_State_Nak
11 Set_Slot_Power_Limit
12 Latency Tolerance Reporting (LTR)
13 Reserved
14 Unlock
15 Vendor_Defined Type 0
16 Vendor_Defined Type 1
17 Invalid Request, Invalid Completion, Page Request, PRG Response

When ATTR_AXISTEN_IF_ENABLE_RX_MSG_INTFC is set to 1, no messages are delivered on the completer request interface. Indications of received message are instead sent through a dedicated receive message interface (see Receive Message Interface).