Clocking - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The Versal Adaptive SoC Integrated Block for PCIe® core clock topology is similar to the AMD UltraScale+ Device Integrated Block for PCIe. You find the phy_clk module in pcie_phy after you generate the PHY IP through the example design or through block automation.