The APB3 (Advanced Peripheral Bus) interface is similar to the DRP interface in previous generations of the programmable logic integrated block for PCIe in earlier architectures.
Note: The APB3 interface is not supported for simulation.
| Port | I/O | Width | Description |
|---|---|---|---|
| apb3_clk | I | 1 | APB3 Clock. The rising edge of PCLK times all transfers on the APB. |
| apb3_paddr |
I |
9 |
APB3 Address. This is the APB address bus (DWORD (32-bit) addresses). It is 9-bit wide and is driven by the peripheral bus bridge unit. |
| apb3_penable | I | 1 | APB3 Enable. This signal indicates the second and subsequent cycles of an APB transfer. |
| apb3_pwdata | I | 32 | APB3 Write Data. This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE is HIGH. This bus can be up to 32 bits wide. |
| apb3_pwrite | I | 1 | APB3 Direction. This signal indicates an APB write access when HIGH and an APB read access when LOW. |
| apb3_psel | I | 1 | APB3 Select. The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required. |
| apb3_prdata | O | 32 | APB3 Read Data. The selected slave drives this bus during read cycles
when PWRITE is LOW. This bus can be up to 32-bits wide. |
| apb3_pready | O | 1 | APB3 Ready. The slave uses this signal to extend an APB transfer. |
| apb3_pslverr | O | 1 | APB3 Slave Error. This signal indicates a transfer failure. |
| apb3_presetn | I | 1 | APB3 Reset This signal indicates an APB reset |